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Applies to: ARM720T
The key point is that the coprocessor has its own pipeline which mimics that of the 7TDMI and you need to take this into account when generating debug sequences. An example sequence might be as follows:
; Readback CP15 Register c2 (TTB) to r0
; fill CP15 instruction pipe
COPROCINST_I 1 MRC p15,0,R0,c2,c0,0
COPROCINST_I 1 NOP
COPROCINST_I 0 NOP
COPROCINST_D 1 00000000
; coprocessor instructions require two execute cycles
;then scan in the next instruction and capture the value
;shifted out on TDO (which is the contents of the TTB).
Note that the supported functionality is limited. You can use scan chain 15 to turn the cache on and off. If you do a system speed load which hits a cache address, you can read values out of the cache, but there is no way of knowing whether the value returned came from the cache or from external memory. Similarly, there is no way to access the cache TAGs, MMU TLB etc.
Article last edited on: 2008-09-09 15:47:37
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