|ARM Technical Support Knowledge Articles|
Applies to: ARM720T
When switching from BCLK -> FCLK (this is always done when the clock is low), in synchronous mode, we just need FCLK to be low. In asynchronous mode, the core waits for the next FCLK falling edge.
Going the other way from FCLK -> BCLK happens when the clock is high.
The MCLK to the 7TDMI core is held high until the next BCLK falling edge.
In general, the average penalty when going from FCLK to BCLK is 1 BCLK phase (assuming a 50/50 duty cycle), in asynchronous mode and 1 FCLK phase when going from BCLK to FCLK. However, systems often have both FCLK & BCLK derived from the same source and are likely to see the same fixed synchronisation penalty every time, which could be anywhere from zero to a full clock cycle, depending upon the phase relationship between the 2 clocks. Running with FCLK = BCLK is disallowed by the datasheet. In practice, it works OK until you approach a clock frequency close to the maximum for the core.
In general, if you want best performance and your code is likely to involve frequent bus accesses, you are likely to see best performance in synchronous mode, as the synchronization penalties are lowest.
Article last edited on: 2008-09-09 15:47:37
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