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What does it mean when the ARM720T model warns of an "Output violation"?

Applies to: ARM720T


The model issues these warnings when an output has changed state, but it is unable to determine which input transition caused the output to change. It is therefore unable to assign a timing path to the output change and the output therefore switches with zero delay - hence the warning being issued.

One common explanation for this is that the model is not being reset correctly. At the start of the simulation, it's necessary for both nTRST and BnRES to go low to reset the internal statetracker of the model.

Article last edited on: 2008-09-09 15:47:37

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