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When comparing interrupt latencies, you need to consider the worst case. If both cores were operating completely out of zero wait-state memory, the 720T interrupt latency would be worse. In both cases, when the interrupt is recognised, the core allows the current instruction to complete. This might be (for example) a LDM (load-multiple) of a long list of registers. In the 720T case, the addresses to be loaded might not be in the cache, triggering a number of cache linefills. The virtual to physical address translation for that memory location might not be cached in the TLB and the write buffer might be full. All of these things would have to be handled before the interrupt service routine could be started. In the 7TDMI case, the addresses being loaded might be in the slowest region of memory and so lots of wait states would be added by the memory system before the interrupt was handled. Which of these 2 things is shorter depends upon your memory system.
In the 720T, you cannot specify that the interrupt routine is placed within the cache - it does not have facilities for lockdown. The code may be marked as cacheable and it may go in the cache, but is not immune from replacement after subsequent linefills. For best performance, it should be in fast memory in both cases.
Article last edited on: 2008-09-09 15:47:37
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