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Applies to: ARM720T
No. The HBURST output of the wrapper is fixed to '001' (INCR). It will never perform a burst transfer of any size. Even for a cache linefill, the AHB HBURST information is not generated, because there is no signal from the core to the wrapper to say that this is a cache linefill.
The 720T core itself can never produce reads or writes of halfwords or bytes on successive cycles - there will always be at least one cycle in between.
E.G. a byte write on the 720T might give an address only cycle followed by a sequential access to the same address. The AHB wrapper would convert that to an AHB Idle cycle followed by an AHB Non-sequential cycle of INCR type.
Article last edited on: 2008-09-09 15:47:37
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