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During simulation we found that the AHB Wrapper HTRANS signal changes both on positive and negative clock edges, but the AHB is a single edge protocol. Why does the wrapper do this? (Rev 0-3)

Applies to: ARM720T


This is a known issue with the 720T AHB wrapper. The problem is that we must wait for the BTRAN value to come out of the core before we can drive the HTRANS signal. There is no way to predict this value (as we can with HADDR), so we have to let it propagate out of the wrapper as soon as possible.

Unfortunately the ASB-AHB timing relationship (BCLK = inverse HCLK) means that HTRANS is not valid until the second half of the HCLK cycle, meaning a much reduced setup time on this input to other AHB blocks. This will probably be the critical path in most ARM7x0T designs, as all other signals will be valid shortly after the HCLK rising edge. Any investigation of timing path problems should probably concentrate on this path.

The only way round this problem would be if the wrapper added a wait state for every cycle so that the core BTRAN output can be sampled and then driven out. However this severely impacts on performance and would not be a reasonable solution. Some customers have worked around this problem by doing things like moving the BCLK edge slightly ahead of the HCLK edge.

Article last edited on: 2008-09-09 15:47:37

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