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Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Applies to: ARM1020/22E, ARM1026EJ-S, ARM1136, ARM720T, ARM920/922T, ARM926EJ-S, ARM940T, ARM946E-S, ARM966E-S


One important reason for making a distinction between a buffered write and an unbuffered write is that when the latter takes place, the core must stop and perform the write, whereas a buffered write will go into the write buffer and many further instructions may be executed before the write takes place.

If writing to one address is likely to change the data read back from a different address with some associated delay or have some other effect on the system (typically when writing to a peripheral register, rather than regular memory) then this is likely to be done as an unbuffered write.

For example, if you have a memory mapped interrupt controller, which has an 'acknowledge' register. The IRQ handler code running on the ARM might write to that acknowledge register, to cause the interrupt request to be removed (take nIRQ) high. It might then re-enable interrupts within the core. If the core had not performed an unbuffered write to the peripheral, it would be possible to write to the register and then re-enable interrupts before the nIRQ signal has gone high - so an interrupt would interrupt itself.

The main reason why a slave device would care about whether it received a buffered write or not is that it might affect the value given on the HRESP[] response signals.

With the exception of the ARM10 cores, pre-architecture v6 ARM cores (e.g. ARM926EJ-S) ignore the AHB ERROR response when a write originated from the write buffer because many instructions may have passed since the STR that caused the ERROR was executed, and these cannot be undone. When a write originated from the ARM cores write buffer, it is always marked as a bufferable access (HPROT[2] is set).

For the reasons explained above, a buffered write cannot (in general) be given an ERROR response on a pre-architecture v6 ARM core, as there is no possibility that the core will take an exception on it. Therefore if a slave received a write with HPROT[2] set, it may wish to perform some other method of letting the core know that an error occurred (e.g. interrupt the core).

Architecture v6 ARM cores (e.g. ARM1136JF-S) and the ARM10 cores can handle imprecise aborts. An ERROR response from a buffered write will cause an abort, but the abort exception handler will not know what instruction caused the abort.

See also:

Article last edited on: 2008-09-09 15:47:37

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