ARM Technical Support Knowledge Articles

What is the implication of not balancing FCLK and HCLK when I lay out my ARM720T design? Are there any implications for synchronous and asynchronous clocking modes?

Applies to: ARM720T


In asynchronous clocking mode, the core makes no assumptions about the relationship between FCLK and BCLK (BCLK being generated from HCLK within the ARM720T AHB wrapper). So, no clock balancing would be required there.

For synchronous mode, the core requires that BCLK only make a transition when FCLK is high. This obviously does have implications for layout, depending upon how the two clocks are generated. If this restriction cannot be guaranteed to be met, asynchronous mode must be used.

Article last edited on: 2008-09-09 15:47:37

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