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What is the test procedure for ARM7EJ-S?

Applies to: ARM7EJ-S


The test methodology for ARM7EJ-S is full scan insertion with ATPG, however the ARM7EJ-S also supports partial scan methodology. If partial scan is used some of the registers are removed from the scan chain (example, the register bank). The main advantage of using partial scan is that it reduces the core area, however at the expense of reduced fault coverage.

The synthesis scripts provide option for scan_ready and scan_inserted netlists. The scan_ready option inserts scannable flip-flops from the technology cell library during compilation. Whereas, the scan_insertion option also inserts scannable flip-flops but then stitches scan chains together.

The supplied scripts allow more than one scan chain to be created if necessary and hence SCANIN & SCANOUT will be busses rather than single lines. Obviously if more than one scan chain is to be used then the extra chip ports will be required for testing.

Article last edited on: 2008-09-09 15:47:37

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