|ARM Technical Support Knowledge Articles|
The ARM946E-S has a von Neumann AHB architecture, and is optimized for running with caches. Therefore it is not as aggressive in its use of the AHB as the other cores. For this reason, you may notice that when the ARM946E-S is executing instructions from main memory with the caches switched off, or from an uncachable area of memory the core will execute instructions at a slower rate.
Unlike the ARM966E-S and the ARM926EJ-S, the ARM946E-S will occasionally use the BUSY transfer type. The details of when this is used can be found in the ARM946E-S Technical Reference Manual.
The ARM946E-S does not perform critical word first loading on cache line fills, and does not use the WRAPx burst types on the AHB.
The ARM966E-S has a von Neumann AHB architecture and does not have caches, so it is optimized to use as much of the AHB idle time as possible for efficient running. It does this with a dedicated instruction preloader block, which acts as a read ahead buffer for instructions (Rev.2 only).
The ARM966E-S Rev.2 does not use BUSY transfer types, but previous versions of the core do.
The ARM966E-S does not use the WRAPx burst types, but it uses all other burst types for efficient data transfer.
The ARM926EJ-S has a Harvard AHB architecture, caches and is a high performance Application Core. It uses the same AHB interface logic as the ARM966E-S achieve high performance over both cached and uncached accesses.
The ARM926EJ-S is incapable of generating a BUSY transfer type.
The ARM926EJ-S can use all burst types for efficient data transfer, but does not use the INCR undefined length burst type.
The ARM926EJ-S is intended for use in a multi-layer AHB system for maximum performance. Some of the external AHB system and memory devices should be accessible by both interfaces at identical address ranges. This is required for literal pool accesses, debugging and the execution of Java code.
Article last edited on: 2008-09-09 15:47:38
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