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How do I lockdown part of my data cache?

Applies to: ARM920/922T, ARM940T


Lockdown is performed with a granularity of one line across each of the 4 cache segments so the smallest quantity of data that can be locked down is 16 words. Each segment of the ARM920T, ARM922T and ARM940T cache comprises 64 lines, lockdown starts at line zero and up to 63 of these lines may be locked down.

Code to perform the lockdown should be held in a non cacheable area of memory, the cache should be enabled and interrupts disabled. Software must ensure that the data to be locked down is not already cached.

The steps are as follows:

  1. Force the data cache victim counter to the line of the cache where lockdown is to begin.
  2. Cause a linefetch of 16 words.
  3. Increment victim counter.
  4. If lockdown is not yet complete return to step 2
  5. Restrict victim counter range.

Below is a short routine for locking down data into the data cache. The routine takes 2 arguments, R0 contains the number of lines to be locked down and will be corrupted , R1 contains the address of where the lockdown is to begin and is preserved.

; Subroutine lock_d_cache
; R1 contains the start address of the data to be locked down
; The subroutine performs a lock-down of data into the D cache
; It first reads the current lock_down index and then locks down
; the number of lines requested.
; Interrupts must be disabled during execution of this routine.
; The data must cause a cache miss for lockdown to succeed.
; The routine should be called via the "BL" instruction
; R0 returns the number of free cache lines remaining, or 0
; if an error occurs.


STMFD R13, {R1-R3} ; save the corrupt registers
BIC R1, R1, #0x3f ; align address to cache line
MRC p15, 0, R2, c9, c0, 0 ; get current data cache index
AND R2, R2, #0x3f ; mask off unwanted bits
ADD R3, R2, R0 ; check to see if current index
CMP R3, #0x3f ; plus line count is greater than 63
; If so branch to error
; as more lines than permitted are
BGT error ; being locked down
ORR R2, R2, #0x80000000 ; set lock bit, R2 contains the
; cache line number to lockdown


MCR p15, 0, R2, c9, c0, 0 ; write lockdown register
LDR R3, [R1], #16 ; loading the first word of a cache
; line causes a complete linefetch
; the base counter R1 is incremented
; to point to the next segment

LDR R3, [R1], #16 ; linefetch segment 1
LDR R3, [R1], #16 ; linefetch segment 2
LDR R3, [R1], #16 ; linefetch segment 3
ADD R2, R2, #0x1 ; increment cache line index
SUBS R0, R0, #0x1 ; decrement line count and set flags
BNE lock_loop ; if the lockdown has completed
; repeat lock down loop
BIC R0, R2, #0x80000000 ; clear lockdown bit
MCR p15, 0, R0, c9, c0, 0 ; restrict victim counter to lines r0 to 63
RSB R0, R0, #64 ; determine how many lines are left
LDMFD R13!, {R1-R3} ; restore registers and return
MOV PC, LR ; R0 contains the number of unlocked lines


MOV R0, #0 ; move 0 into R0 to indicate error
LDMFD R13!, {R1-R3} ; restore corrupted registers and
MOV PC, LR ; return

See also:

Article last edited on: 2008-09-09 15:47:38

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