|ARM Technical Support Knowledge Articles|
The main consideration when designing with the ARM clock should be not to violate the minimum HIGH pulse width or the minimum LOW pulse width.
Let's take the example where an ARM7TDMI has been characterized as being able to run at a maximum frequency of 90MHz.
___________<-- 5.55ns ->__________ ___
MCLK ___/ \___________/ \__________/
<-- 5.55ns ->
Assuming that there is a 50 percent duty cycle, the minimum LOW and HIGH pulse width will be 5.55ns each.
If this clock was then run at 32MHz (31.25ns period) then there would be no problems varying the duty cycle anywhere between the two following diagrams:
__________ <----------- 25.7ns ------------> __________
MCLK __/ \_________________________________/ \_____
<- 5.55ns ->
__<- 5.55 ns->_________________________________ ______
MCLK \__________/ \__________/
<----------- 25.7ns ------------>
As long as you do not violate the minimum high or low pulse width of the clock, you can have any clock duty cycle you want.
Synthesizable designs only operate off the rising edge of the clock and so are only sensitive to violating the minimum clock period. The hard macrocells utilize both the rising and the falling edge of the clock and so consideration must be given to both the HIGH and LOW pulse widths.
Note about the ARM720T Rev.4:
It is mandatory to have a 50/50 duty cycle on the ARM720T Rev.4. This design uses both edges and any variation in duty cycle will impact your designs maximum operating frequency.
Article last edited on: 2008-09-09 15:47:38
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