ARM Technical Support Knowledge Articles

What might an initial configuration of the ARM7TDMI look like?

Applies to: ARM7TDMI

Answer

Example initial configuration of the ARM7TDMI input signals:

Signal
State
Description
Remarks
MCLKDrivenMemory Clock InputMust be actively driven. If held static, processor stops without loss of state.
ABEHIGHAddress Bus EnableIf HIGH, Address bus enabled. If LOW, Address bus is put in a high impedance state
DBEHIGHData Bus EnableIf HIGH, Data bus enabled. If LOW, Data bus is put into a high impedance state
TBEHIGHTest Bus EnableEnables data bus and address bus. Should be held HIGH under normal conditions. If LOW, Address bus, data bus, LOCK, MAS, nTRANS, nRW and nOPC are forced to high impedance state.
nENINLOWNot Enable InputMay be used with nENOUT to control the data bus during write cycles
DBGENHIGHDebug EnableIMPORTANT! Must be high to allow the use of debug features and Multi-ICE or EmbeddedICE
DBGRQLOWDebug RequestIf high, the ARM7TDMI enters debug state after executing the current instruction.
BREAKPTLOWBreakpointIf high, the current memory access is breakpointed. Should be LOW for normal execution.
EXTERN(1,0)HIGH / LOWExternal inputAllows breakpoints or watchpoints to be dependent on external conditions. Not used by debugger, by default.
CPAHIGHCoprocessor AbsentIMPORTANT! Should always be HIGH unless external coprocessor is present
CPBHIGHCoprocessor busyIMPORTANT! Should always be HIGH unless external coprocessor is present.
ISYNCLOWSynchronous InterruptsIMPORTANT! If LOW, nIRQ and nFIQ interrupts are synchronised internally by the ARM core
BUSENHIGH / LOWData Bus configurationIf HIGH, the unidirectional data buses are used, and the bi-directional data bus must be left unconnected. If LOW, the bi-directional data bus is used. DIN[31:0] must be tied off, and DOUT[31:0] can be left unconnected.
DIN[31:0]HIGH / LOWData InTied off to either state if BUSEN is LOW and therefore the bidirectional bus is used. Driven by system if BUSEN is HIGH.
D[31:0]HIGH / LOWBidirectional Data BusUsed by the system if BUSEN is LOW. IMPORTANT! Has to be left unconnected if BUSEN is HIGH
BIGENDHIGH / LOWBig EndianHIGH if system has Big Endian configuration, LOW if Little Endian configuration is used.
ALEHIGHAddress Latch EnableUsed to control the transparent latches on the address bus, when reading from byte wide memory. If LOW, address is frozen.
APEHIGHAddress Pipeline EnableIf HIGH allows the address bus to be pipelined, if LOW, address is put on the address bus in phase 1 of the actual cycle.
BL[3:0]HIGHByte Latch ControlControls when data and instructions are latched from the external data bus. If HIGH, data are latched on the falling edge of MCLK.
ABORTLOWMemory AbortIf HIGH tells the memory system that a requested access is not allowed.
nIRQHIGHNot Interrupt RequestMust be taken LOW to interrupt the processor. Appropriate disable bit must be clear.
nFIQHIGHNot Fast Interrupt RequestMust be taken LOW to interrupt the processor. Appropriate disable bit must be clear.
nWAITHIGHnot WaitnWAIT is ANDed with MCLK and must only change when MCLK is LOW. Must be tied HIGH if not used
nRESETLOW for Resetnot ResetHas to be driven LOW for at least two MCLK cycles, with nWAIT held high in order to properly reset the core.
nTRSTLOWnot Test ResetMay be tied to LOW if debug/test logic is not to be used. Has to be connected to a pad if JTAG test methodology is used.
SDOUTBSLOWBoundary Scan Serial Output DataShould be tied to LOW if no external scan chains are supplied.
TDIHIGHTest Data InputShould be held HIGH if TAP controller is not active.
TMSHIGHTest Mode SelectShould be held HIGH if TAP controller is not active.
TCKHIGHTest Data OutputShould be held HIGH if TAP controller is not active.

Article last edited on: 2008-09-09 15:47:38

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