What might an initial configuration of the ARM7TDMI look like?

Applies to: ARM7TDMI

Answer

Example initial configuration of the ARM7TDMI input signals:

Signal	State	Description	Remarks
MCLK	Driven	Memory Clock Input	Must be actively driven. If held static, processor stops without loss of state.
ABE	HIGH	Address Bus Enable	If HIGH, Address bus enabled. If LOW, Address bus is put in a high impedance state
DBE	HIGH	Data Bus Enable	If HIGH, Data bus enabled. If LOW, Data bus is put into a high impedance state
TBE	HIGH	Test Bus Enable	Enables data bus and address bus. Should be held HIGH under normal conditions. If LOW, Address bus, data bus, LOCK, MAS, nTRANS, nRW and nOPC are forced to high impedance state.
nENIN	LOW	Not Enable Input	May be used with nENOUT to control the data bus during write cycles
DBGEN	HIGH	Debug Enable	IMPORTANT! Must be high to allow the use of debug features and Multi-ICE or EmbeddedICE
DBGRQ	LOW	Debug Request	If high, the ARM7TDMI enters debug state after executing the current instruction.
BREAKPT	LOW	Breakpoint	If high, the current memory access is breakpointed. Should be LOW for normal execution.
EXTERN(1,0)	HIGH / LOW	External input	Allows breakpoints or watchpoints to be dependent on external conditions. Not used by debugger, by default.
CPA	HIGH	Coprocessor Absent	IMPORTANT! Should always be HIGH unless external coprocessor is present
CPB	HIGH	Coprocessor busy	IMPORTANT! Should always be HIGH unless external coprocessor is present.
ISYNC	LOW	Synchronous Interrupts	IMPORTANT! If LOW, nIRQ and nFIQ interrupts are synchronised internally by the ARM core
BUSEN	HIGH / LOW	Data Bus configuration	If HIGH, the unidirectional data buses are used, and the bi-directional data bus must be left unconnected. If LOW, the bi-directional data bus is used. DIN[31:0] must be tied off, and DOUT[31:0] can be left unconnected.
DIN[31:0]	HIGH / LOW	Data In	Tied off to either state if BUSEN is LOW and therefore the bidirectional bus is used. Driven by system if BUSEN is HIGH.
D[31:0]	HIGH / LOW	Bidirectional Data Bus	Used by the system if BUSEN is LOW. IMPORTANT! Has to be left unconnected if BUSEN is HIGH
BIGEND	HIGH / LOW	Big Endian	HIGH if system has Big Endian configuration, LOW if Little Endian configuration is used.
ALE	HIGH	Address Latch Enable	Used to control the transparent latches on the address bus, when reading from byte wide memory. If LOW, address is frozen.
APE	HIGH	Address Pipeline Enable	If HIGH allows the address bus to be pipelined, if LOW, address is put on the address bus in phase 1 of the actual cycle.
BL[3:0]	HIGH	Byte Latch Control	Controls when data and instructions are latched from the external data bus. If HIGH, data are latched on the falling edge of MCLK.
ABORT	LOW	Memory Abort	If HIGH tells the memory system that a requested access is not allowed.
nIRQ	HIGH	Not Interrupt Request	Must be taken LOW to interrupt the processor. Appropriate disable bit must be clear.
nFIQ	HIGH	Not Fast Interrupt Request	Must be taken LOW to interrupt the processor. Appropriate disable bit must be clear.
nWAIT	HIGH	not Wait	nWAIT is ANDed with MCLK and must only change when MCLK is LOW. Must be tied HIGH if not used
nRESET	LOW for Reset	not Reset	Has to be driven LOW for at least two MCLK cycles, with nWAIT held high in order to properly reset the core.
nTRST	LOW	not Test Reset	May be tied to LOW if debug/test logic is not to be used. Has to be connected to a pad if JTAG test methodology is used.
SDOUTBS	LOW	Boundary Scan Serial Output Data	Should be tied to LOW if no external scan chains are supplied.
TDI	HIGH	Test Data Input	Should be held HIGH if TAP controller is not active.
TMS	HIGH	Test Mode Select	Should be held HIGH if TAP controller is not active.
TCK	HIGH	Test Data Output	Should be held HIGH if TAP controller is not active.

Article last edited on: 2008-09-09 15:47:38

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