ARM Technical Support Knowledge Articles

What might an initial configuration of the ARM9TDMI look like?

Applies to: ARM9TDMI

Answer

Example initial configuration of the ARM9TDMI input signals:

Signal
State
Description
Remarks
DABORTDRIVENData AbortIf not used DABORT must be LOW to avoid causing the core taking a data abort exception.
IABEHIGHInstruction Address Bus EnableIf HIGH the address bus enabled.
If LOW the address bus is set to high impedance.
IABORTDRIVENInstruction AbortIf not used IABORT must be LOW to avoid causing the core taking an instruction abort exception.
ID[31:0]DRIVENInstruction Data BusWhen nRESET is taken HIGH, ID[31:0] will be undefined for 3 GCLK cycles.
DD[31:0]DRIVENData Data BusWhen UNIEN is LOW, DD[31:0] operates as a bidirectional databus.
When UNIEN is HIGH DD[31:0] operates as a unidirectional output bus.
DABEHIGHData Adrress Bus EnableWhen LOW, DA[31:0] will be high impedance. Has same effect on DnTRANS, DLOCK, DMAS[1:0], DnRW and DnM[4:0]. If UNIEN is HIGH, DABE is ignored.
DDBEHIGHData Data Bus EnableWhen LOW, DA[31:0] will be high impedance.
If UNIEN is HIGH, DABE is ignored.
DDIN[31:0]DRIVENData Input BusTied off to either state if UNIEN is LOW and therefore the bidirectional bus is used. Driven by the system if UNIEN is HIGH.
CHSD[1:0]DRIVENCoprocessor Handshake DecodeIf no coprocessor is present in the system then CHSD[1] should be tied HIGH and CHSD[0] should be tied LOW.
CHSE[1:0]DRIVENCoprocessor Handshake ExecuteIf no coprocessor is present in the system then CHSE[1] should be tied HIGH and CHSE[0] should be tied LOW.
SDOUTBSDRIVENBoundary Scan Serial Output DataShould be tied LOW if no external boundary scan chain is connected.
TAPID[31:0]DRIVENTAP IdentificationCaptured when using the IDCODE instruction on the TAP controller state machine.
TCKHIGHJTAG Clock (Test Clock)Should be held HIGH if TAP controller is not active.
TDIHIGHTest Data Input (JTAG Serial Input)Should be held HIGH if TAP controller is not active.
TMSHIGHTest Mode SelectShould be held HIGH if TAP controller is not active.
nTRSTHIGHNot Test ResetThis pin must be pulsed or driven LOW after power up to achieve normal device operation.
DBGENHIGHDebug EnableShould be driven HIGH if debugging is required.
DEWPTLOWData WatchpointIf HIGH, the ARM9TDMI takes a watchpoint and enters debug state.
EDBGRQLOWExternal Debug RequestWhen driven HIGH, this causes the processor to enter debug state after execution of the current instruction completes.
EXTERN0DRIVENExternal Debug RequestAllows breakpoints or watchpoints to be dependent on external conditions.
Not used by default with the debugger.
EXTERN1DRIVENExternal Debug RequestAllows breakpoints or watchpoints to be dependent on external conditions.
Not used by default with the debugger.
IEBKPTLOWInstruction BreakpointIf HIGH, the ARM9TDMI takes a breakpoint and enters debug state.
TBEHIGHTest Bus EnableWhen LOW, the following signals are high impedance: DD[31:0], DA[31:0], DLOCK, DMAS[1:0], DnM[4:0], DnRW, DnTRANS, DMORE, DnMREQ, DSEQ, IA[31:0], InM[4:0], InTRANS, InMREQ, ISEQ, ITBIT, LATECANCEL and PASS.
Under normal conditions TBE should be HIGH. Ignored if UNIEN is HIGH.
BIGENDDRIVENBig Endian ConfigurationWhen HIGH, memory is treated as big-endian format.
When LOW, memory is treated as little-endian format.
nFIQHIGHNot Fast InterruptLevel sensitive, so must be held LOW until suitable response is received.
May be synchronous or asynchronous, depending on ISYNC.
GCLKDRIVENClockThis clock times all ARM9TDMI memory accesses and internal operations. May be stretched to allow access to slow memory or peripherals. Alternatively, nWAIT can be used to stretch phase 2 of GCLK.
HIVECSDRIVENHigh Vectors ConfigurationWhen LOW, exception vectors start at 0x00000000.
When HIGH, exception vectors start at 0xFFFF0000.
nIRQHIGHNot Interrupt RequestAs nFIQ, but with lower priority.
ISYNCDRIVENSynchronous InterruptsWhen LOW, nIRQ and nFIQ are synchronised.
When HIGH, interrupts must be applied synchronously with respect to GCLK.
nRESETLOWNot ResetLevel sensitive input signal used to start ARM9TDMI from known address.
ARM9TDMI asynchronously enters reset when nRESET goes LOW.
nWAITHIGHNot WaitUsed to stretch phase 2 of GCLK. If not used then it must be tied HIGH.
nWAIT can only change when GCLK is HIGH.
UNIENDRIVENUnidirectional EnableWhen HIGH, all ARM9TDMI outputs are permanently driven. DDIN[31:0] and DD[31:0] form a unidirectional data bus. When LOW, outputs can go tristate and the DD[31:0] bus is only driven during write cycles. If DD[31:0] and DDIN[31:0] are wired together they form a bidirectional data bus.

Article last edited on: 2008-09-09 15:47:38

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