|ARM Technical Support Knowledge Articles|
Applies to: ARM9TDMI
Example initial configuration of the ARM9TDMI input signals:
|DABORT||DRIVEN||Data Abort||If not used DABORT must be LOW to avoid causing the core taking a data abort exception.|
|IABE||HIGH||Instruction Address Bus Enable||If HIGH the address bus enabled.|
If LOW the address bus is set to high impedance.
|IABORT||DRIVEN||Instruction Abort||If not used IABORT must be LOW to avoid causing the core taking an instruction abort exception.|
|ID[31:0]||DRIVEN||Instruction Data Bus||When nRESET is taken HIGH, ID[31:0] will be undefined for 3 GCLK cycles.|
|DD[31:0]||DRIVEN||Data Data Bus||When UNIEN is LOW, DD[31:0] operates as a bidirectional databus.|
When UNIEN is HIGH DD[31:0] operates as a unidirectional output bus.
|DABE||HIGH||Data Adrress Bus Enable||When LOW, DA[31:0] will be high impedance. Has same effect on DnTRANS, DLOCK, DMAS[1:0], DnRW and DnM[4:0]. If UNIEN is HIGH, DABE is ignored.|
|DDBE||HIGH||Data Data Bus Enable||When LOW, DA[31:0] will be high impedance.|
If UNIEN is HIGH, DABE is ignored.
|DDIN[31:0]||DRIVEN||Data Input Bus||Tied off to either state if UNIEN is LOW and therefore the bidirectional bus is used. Driven by the system if UNIEN is HIGH.|
|CHSD[1:0]||DRIVEN||Coprocessor Handshake Decode||If no coprocessor is present in the system then CHSD should be tied HIGH and CHSD should be tied LOW.|
|CHSE[1:0]||DRIVEN||Coprocessor Handshake Execute||If no coprocessor is present in the system then CHSE should be tied HIGH and CHSE should be tied LOW.|
|SDOUTBS||DRIVEN||Boundary Scan Serial Output Data||Should be tied LOW if no external boundary scan chain is connected.|
|TAPID[31:0]||DRIVEN||TAP Identification||Captured when using the IDCODE instruction on the TAP controller state machine.|
|TCK||HIGH||JTAG Clock (Test Clock)||Should be held HIGH if TAP controller is not active.|
|TDI||HIGH||Test Data Input (JTAG Serial Input)||Should be held HIGH if TAP controller is not active.|
|TMS||HIGH||Test Mode Select||Should be held HIGH if TAP controller is not active.|
|nTRST||HIGH||Not Test Reset||This pin must be pulsed or driven LOW after power up to achieve normal device operation.|
|DBGEN||HIGH||Debug Enable||Should be driven HIGH if debugging is required.|
|DEWPT||LOW||Data Watchpoint||If HIGH, the ARM9TDMI takes a watchpoint and enters debug state.|
|EDBGRQ||LOW||External Debug Request||When driven HIGH, this causes the processor to enter debug state after execution of the current instruction completes.|
|EXTERN0||DRIVEN||External Debug Request||Allows breakpoints or watchpoints to be dependent on external conditions.|
Not used by default with the debugger.
|EXTERN1||DRIVEN||External Debug Request||Allows breakpoints or watchpoints to be dependent on external conditions.|
Not used by default with the debugger.
|IEBKPT||LOW||Instruction Breakpoint||If HIGH, the ARM9TDMI takes a breakpoint and enters debug state.|
|TBE||HIGH||Test Bus Enable||When LOW, the following signals are high impedance: DD[31:0], DA[31:0], DLOCK, DMAS[1:0], DnM[4:0], DnRW, DnTRANS, DMORE, DnMREQ, DSEQ, IA[31:0], InM[4:0], InTRANS, InMREQ, ISEQ, ITBIT, LATECANCEL and PASS.|
Under normal conditions TBE should be HIGH. Ignored if UNIEN is HIGH.
|BIGEND||DRIVEN||Big Endian Configuration||When HIGH, memory is treated as big-endian format.|
When LOW, memory is treated as little-endian format.
|nFIQ||HIGH||Not Fast Interrupt||Level sensitive, so must be held LOW until suitable response is received.|
May be synchronous or asynchronous, depending on ISYNC.
|GCLK||DRIVEN||Clock||This clock times all ARM9TDMI memory accesses and internal operations. May be stretched to allow access to slow memory or peripherals. Alternatively, nWAIT can be used to stretch phase 2 of GCLK.|
|HIVECS||DRIVEN||High Vectors Configuration||When LOW, exception vectors start at 0x00000000.|
When HIGH, exception vectors start at 0xFFFF0000.
|nIRQ||HIGH||Not Interrupt Request||As nFIQ, but with lower priority.|
|ISYNC||DRIVEN||Synchronous Interrupts||When LOW, nIRQ and nFIQ are synchronised.|
When HIGH, interrupts must be applied synchronously with respect to GCLK.
|nRESET||LOW||Not Reset||Level sensitive input signal used to start ARM9TDMI from known address.|
ARM9TDMI asynchronously enters reset when nRESET goes LOW.
|nWAIT||HIGH||Not Wait||Used to stretch phase 2 of GCLK. If not used then it must be tied HIGH.|
nWAIT can only change when GCLK is HIGH.
|UNIEN||DRIVEN||Unidirectional Enable||When HIGH, all ARM9TDMI outputs are permanently driven. DDIN[31:0] and DD[31:0] form a unidirectional data bus. When LOW, outputs can go tristate and the DD[31:0] bus is only driven during write cycles. If DD[31:0] and DDIN[31:0] are wired together they form a bidirectional data bus.|
Article last edited on: 2008-09-09 15:47:38
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