|ARM Technical Support Knowledge Articles|
Applies to: ARM7TDMI
This document describes how the serialised test vectors should be applied to the ARM7TDMI Test Chip.
The serialised tests consist of eight modules:
Test Vector File Format
The serialised pattern files contain just the test inputs nTRST, TCK, TMS and TDI and the test output TDO, as shown below.
T X X X | X
r T T T | T
s c m d | d
t k s i | o
L H H L | . } 0 Reset
L H H L | . } 100 Reset
Applying serialised vectors, using BUSDIS
Revision 1 and all later revisions of the ARM7TDMI implement a signal called BUSDIS, which goes active (high) early in the sequence of serialised vectors. This signal may be used to prevent the system from driving onto the ARM during testing.
However, BUSDIS does not stay active for the duration of the serialised test vectors, and so it must be latched. The latched version is then used to keep the rest of the system inactive. For example, this can be OR'ed with nMREQ, such that the system sees nMREQ_SYSTEM as being held high during testing, even if nMREQ changes.
The latch can be cleared down only by nRESET, as it is reasonable to assume that the device will be reset after testing, before it is expected to function correctly.
The additional logic to implement this between the ARM and the system could be:
|0||1||X||1||1 (see note 1)|
|1||0||B||0||B (see note 2)|
|1||0||X||1||1 (see note 3)|
|0||0||C||0||C (see note 4)|
Using this approach, TBE must be high for the EmbeddedICE logic test, and can be high for all other tests if required. There is no longer a requirement to drive TBE low for testing.
Article last edited on: 2008-09-09 15:47:38
Did you find this article helpful? Yes No
How can we improve this article?