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What is the ARM7TDMI Serialised Test Procedure?

Applies to: ARM7TDMI

Answer

Introduction

This document describes how the serialised test vectors should be applied to the ARM7TDMI Test Chip.

The serialised tests consist of eight modules:

  1. ARM serial test vectors
  2. Multiplier serial test vectors
  3. Thumb serial test vectors
  4. Pipe serial test vectors
  5. ALE serial test vectors
  6. Debug serial test vectors
  7. EmbeddedICE logic serial test vectors
  8. RegNew serial test vectors

Test Vector File Format

The serialised pattern files contain just the test inputs nTRST, TCK, TMS and TDI and the test output TDO, as shown below.

   --------|---
X |
N |
T X X X | X
r T T T | T
s c m d | d
t k s i | o
--------|---
|
--------|---
L H H L | . } 0 Reset
L H H L | . } 100 Reset

Applying serialised vectors, using BUSDIS

Revision 1 and all later revisions of the ARM7TDMI implement a signal called BUSDIS, which goes active (high) early in the sequence of serialised vectors. This signal may be used to prevent the system from driving onto the ARM during testing.

However, BUSDIS does not stay active for the duration of the serialised test vectors, and so it must be latched. The latched version is then used to keep the rest of the system inactive. For example, this can be OR'ed with nMREQ, such that the system sees nMREQ_SYSTEM as being held high during testing, even if nMREQ changes.

The latch can be cleared down only by nRESET, as it is reasonable to assume that the device will be reset after testing, before it is expected to function correctly.

The additional logic to implement this between the ARM and the system could be:

ARM7TDMI Serialised Test Procedure
nRESETBUSDISnMREQBUSDIS_LATCHEDnMREQ_SYSTEM
01X11 (see note 1)
00A0A
10B0B (see note 2)
11X11
10X11 (see note 3)
00C0C (see note 4)

Notes:

  1. This condition may occur momentarily before the ARM is fully reset.
  2. System operating normally - BUSDIS has not yet gone high.
  3. BUSDIS has previously been high, and nMREQ_SYSTEM is kept high.
  4. Testing has completed, and device is reset prior to normal use.

Using this approach, TBE must be high for the EmbeddedICE logic test, and can be high for all other tests if required. There is no longer a requirement to drive TBE low for testing.

All Tests

  1. nRESET shall be tied to VDD for test duration.
  2. MCLK shall be tied to VSS for test duration.
  3. TBE shall be tied to VDD for test duration
  4. BUSDIS should be latched, and used to prevent the system driving onto the following signals during testing:
    1. A[31:0]
    2. D[31:0]
    3. nOPC
    4. nRW
    5. MAS[1:0]
    6. nTRANS
  5. All other inputs are don't cares.
  6. The CTRM file arm7tdmir1_ser_p0.ctrm describes the relevant signal timings.

Attachments: img1920.gif

Article last edited on: 2008-09-09 15:47:38

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