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Note: This FAQ does not apply to any of ARMs synthesizable (-S) processor cores. A separate FAQ covering these cores is currently being written.
If the designer wants to test additional devices on the ASIC, either scan chain 3 (boundary scan) can be used, or additional scan chains can be added:
The ARM7TDMI uses scan chains 0-4, 8 for internal purposes. Additionally, scan chain 15 is used by the system control coprocessor in the ARM720T, and scan chain 6 is used by the Embedded Trace Macrocell (ETM). Therefore, for the ARM7 family, scan chains 5, 7 and 10-14 can be used by the ASIC designer to test additional parts of the system.
For the ARM9 family, scan chains 16 to 31 can be used, while scan chains 0 to 15 are reserved for use by ARM.
Note: The ARM TAP controller is IEEE compliant. It is recommended to follow the IEEE1149.1 specifications when adding scan chains to the TAP Controller.
Latch-based scan cells similar to the following are used:
Latch A has two controlling inputs, SHCLKBS and ECAPCLKBS. It is effectively 2 latches, with a mux which selects whichever clock most recently changed. SHCLKBS and ECAPCLKBS are mutually exclusive signals.
The signals the designer needs to use for the BS cells are:
DRIVEBS (Equivalent to IEEE1149 signal) DriveOut
SDINBS 'From last cell' to first cell in chain
SDOUTBS 'To next cell' from last cell in chain
If you are adding other scan chains (as opposed to just adding a boundary scan chain on scan-chain 3), you will also need to decode equivalent control signals from:
SCREG[3:0] number of scan chain currently selected
IR[3:0] TAP controller instruction register
TAPSM[3:0] TAP controller state machine
TCK1 test clock phase 1
TCK2 test clock phase 2
SDINBS data out of ARM core into scan chain
SDOUTBS data output from scan chain
(will need mux'ing with other scan chains)
Note that the ARM7TDMI is a latch-based design, and it is assumed that any additional scan cells will be latch-based, too. Latch-based scan cells are discussed in the JTAG specification, IEEE1149.1 Appendix A.
If a D-Types rather than a latch-based design is used, the designer probably might want to ignore SDINBS and use TDI instead (SDINBS is simply the output of a D-type with TDI at the input, clocked by TCK)
The timing of the boundary scan control signals (when in EXTEST), is:
Note the extra pulse on SHCLK2BS.
All ARM core models show the correct behaviour of the TAP Controller, so it is possible to determine the behaviour in more detail from simulations, if necessary.
Some other inputs and outputs related to JTAG & TAP controller are also provided, but these are not strictly JTAG signals. They are provided to make it easier to re-use the TAP controller to add scan chains and to implement an external boundary scan chain for the ASIC.
Multiplexing of JTAG pins:
With 2 TAP controllers, there are 3 possibilities:
Article last edited on: 2008-09-09 15:47:38
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