ARM Technical Support Knowledge Articles

Why does the DSM CPSR contain X values after changing nIRQ/nFIQ inputs?

Applies to: Processor Cores


There are two possible reasons for this:

  1. You have not held the interrupt active until the processor has entered the appropriate execption mode. See "Are the IRQ and FIQ interrupts level-sensitive?"
  2. You may have changed the CPSR  interrupt flags at around the same time as the interrupt input. See "What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?"

Article last edited on: 2008-09-09 15:47:39

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