|ARM Technical Support Knowledge Articles|
Applies to: Processor Cores
Most of the DSMs are based on the RTL description which is compiled into a Swift model. Therefore X state handling in the DSM is dependent on the RTL. In some cases the RTL contains statments to monitor for X values and some do not. EG the ARM7TDMI will issue ASSERTION warnings when X values are written to an ARM register, while the ARM946 gives very little in the way of warnings (it is best to check the EIS trace should you suspect an X related problem with this processor).
In some cached cores,such as ARM922T, integers are used to model the memory locations for the sake of simulation speed. This is done on a per nibble basis (ie a nibble is translated into an integer) If a particular nibble contains an X then the previous value is retained and a warning is issued from the RTL code. Unfortunately this warning message doesn’t make it out of the DSM and into the simulation log, making them difficult to spot.
Article last edited on: 2008-09-09 15:47:39
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