ARM Technical Support Knowledge Articles

Can I preload caches and registers with data?

Applies to: Processor Cores


No. The DSM is designed to reflect the behaviour of the real silicon. It is generated from the RTL used by the core designers. Since one would not be able to preload registers or caches in the real silicon this behaviour is not available in the DSM.

Article last edited on: 2008-09-09 15:47:39

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