|ARM Technical Support Knowledge Articles|
For general information about the JTAG synchronisation logic and debugging with adaptive clocking, please see the following FAQ entries:
Whereas in most ARM cores DBGTDO changes when DGBTCKEN is high, in ARM11 DBGTDO changes one cycle after DBGTCKEN is high. For this reason the ARM11 JTAG synchronisation logic is different from other cores.
The best scenario to debug the ARM11 would be to have a TCK high period equal to 3 core clock periods, and a TCK low period equal to 4 core clock periods, which sets a maximum TCK frequency less than one seventh of the core clock frequency.
With a 50% duty cycle the maximum TCK frequency is one eigth of the core clock frequency.
Article last edited on: 2011-11-04 17:19:32
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