ARM Technical Support Knowledge Articles

General questions about Versatile logic tiles

Applies to: Versatile Logic Tiles

Answer

[Version 1.1.1 - updated 11 Oct 04 - includes Versatile/PB926EJ-S pinout and fixes in spreadsheet]

The primary feature of a logic tile is the large, uncommitted FPGA which can be used to prototype custom IP. Logic tiles may be stacked to provide additional capacity. Logic tiles can be used with the Versatile/PB926EJ-S baseboard, or with the Integrator/AP and CP motherboards if an additional interface module (IM-LT1) is present. Logic tiles can also be used standalone when powered from the IM-LT1 board.

The logic tile FAQ is available as a Zip file containing two files -

  1. The FAQ document in PDF format, which contains questions such as:

    • What is a Logic Tile (LT-XC2V4000+)?
    • What is an Interface Module (IM-LT1 / IM-LT2)?
    • How many logic tiles can I stack together?
    • Can I stack a core module and a logic tile without an AP motherboard?
    • Can I stack an IM-PD1 or IM-AD1 on top of a Logic Tile?
    • How can I build my own board and stack it on top of a logic tile?

  2. A Microsoft Excel spreadsheet which shows the signal routing between the logic tile header connectors and FPGA I/Os. Also shown are connections between the tile FPGA and an Integrator/AP (or CP) motherboard when the tile is connected to the motherboard via an IM-LT1 interface module.

Download here (110KB Zip)

Attachments: logic_tile_faq_v1_1_1.zip

Article last edited on: 2009-01-20 15:26:21

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential