|ARM Technical Support Knowledge Articles|
The DSTREAM / RVI Code Sequence mechanism offers similar functionality to the Multi-ICE Cache Clean Code.
When debugging cached cores, the debug hardware (i.e. DSTREAM or RVI unit) needs to maintain cache coherency during debug operations. For most cached cores this can be performed transparently over JTAG, but for certain cores a small code sequence needs to be run on the target to perform a data cache clean.
The only cores that require a code sequence to be run for cache cleaning are the ARM940T and ARM946E-S, and it will only be required for cores operating in Write Back caching mode.
Code Sequences may also be required by other cores to perform certain co-processor operations requested from within the debugger.
The protocol used to access the Code Sequence Area on the target supports word, halfword and byte accesses, but current implementations only make word accesses to the memory.
The ARM documentation lists the following requirements for Code Sequence Memory Areas:
- unused by the target
- readable and writable (See note 1 below)
- non-cacheable (for cached targets) (See note 2 below)
- at least 128 bytes in size.
(1) For cores that support memory protection via a Memory Protection Unit (MPU) or a Memory Management Unit (MMU), some further explanation is required.
If debugging with the RealView ICE option "Bypass memory protection when in debug" selected, then the Code Sequence Address *can* be set to an area of memory that is protected by the MMU or MPU.
For cores with an MMU, there is still a requirement that this area of memory is defined within the MMU translation tables.
(2) The Code Sequence address *can* be placed in memory with a cacheable attribute provided that the area of memory chosen is not currently cached. An area of memory outside application code and data areas should be a safe choice.
Article last edited on: 2011-11-02 16:20:59
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