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Applies to: Integrator
[Updated 11 July 2006]
This FAQ applies to Integrator/CM1136JF-S boards with test chips marked either:
(Earlier test chip) (Later test chip)
Test chip SRAMs
The test chip used on the Integrator/CM1136JF-S incorporates some internal SRAMs (in addition to the TCMs in the ARM1136JF-S core itself). There are 2 banks of SRAM called 'Primary test chip RAM', and a single bank of 'Secondary test chip RAM'. It has been found that on both of these test chip types, all three of these SRAM areas exhibit random data corruption failures when accessed by code running on the test chip.
Test chip PLL
These test chips include a Phase Locked Loop (PLL), the purpose of which is to to multiply the relatively slow clock input from the board up to a higher frequency for the ARM1136JF-S core - the maximum stable operating frequency of the core is approximately 350MHz.
The PLL in the later ARM1136JF-S test chip (date codes 0439 or 0411) works correctly. Unfortunately, the PLL circuit in the '0344' test chip does not function properly and cannot be used, so the Core Module's on-board programmable clock oscillator must generate the full clock frequency used by the core. The datasheet for the generator chip (ICS307) gives the maximum frequency as 200MHz under worst-case conditions. However, we have successfully tested the ARM1136 core with the ICS307 generating 256MHz.
Alternatively, it may be possible to modify the board to inject a faster clock source from an external signal generator. This has not been tested by ARM.
It is not possible for ARM to exchange these Core Modules on the grounds that the SRAM does not work, or that the PLL does not work in the case of the '0344' chip. These are examples of test chip functionality that is subject to change between batches, and should be documented in the release notes document that shipped with the board. Please see the FAQ: Features and performance of ARM test chips are subject to change for further information.
Article last edited on: 2009-02-10 17:26:55
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