ARM Technical Support Knowledge Articles

What cache sizes can be used in the ARM926EJ-S Macrocell?

Applies to: ARM926EJ-S


Applies to: ARM926EJ-S

In the ARM926EJ-S, cache sizes from 4-128 KBytes are supported. Cache sizes must be a power of two.

You must have at least 4KBytes of Instruction and Data Cache, it is no problem to have different Instruction/Data cache sizes.

If you don't need caches, this is not supported by the ARM926EJ-S (caches are required by the Memory Management Unit), you could use an ARM946E-S (this uses a Memory Protection Unit), a cached processor that supports 0KB caches, or the ARM966E-S or ARM968E-S which are compact cores that provide Tightly Coupled Memory support only.

See also:

Article last edited on: 2008-09-09 15:47:43

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential