|ARM Technical Support Knowledge Articles|
Applies to: Processor Cores
To configure the DSM, you must modify the component instanciation of the core, by adding the lines of the required generic(s) Verilog 'defparam' mappings.
The code fragment below is an example of setting an ARM926EJS to have a 16K instruction cache, and a 32K data cache.
If the ARM926EJS model is instantiated as theARM926EJS, add the following:
defparam theARM926EJS.ICACHE_SIZE = 16384 ; // size in bytes defparam theARM926EJS.DCACHE_SIZE = 32768 ; // size in bytes defparam theARM926EJS.DisableBlkClkGate = 0; // gated clock not disabled // COMPONENT INSTANTIATION ARM926EJS theARM926EJS (HADDR, ... etc ... )
Article last edited on: 2008-09-09 15:47:44
Did you find this article helpful? Yes No
How can we improve this article?