ARM Technical Support Knowledge Articles

Can the WVALID signal for a write transfer be active before the AWVALID? If so, how does the interconnect know which slave the transfer is for?

Applies to: AXI


Whilst it is generally expected that WVALID will only be asserted at the same or after AWVALID, there can be cases when WVALID is asserted before AWVALID. For example this can occur when the address channel includes a buffer or when the signals are crossing an asynchronous boundary.

Article last edited on: 2008-09-09 15:47:44

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