ARM Technical Support Knowledge Articles

Why is the VALID signal sticky?

Applies to: AXI


The main advantage of keeping a VALID signal constant (and the associated information, such as address) is that it can remove the need to put additional registering in some places. For example, the APB bridge can just use the READY signal to hold the address stable for 2 cycles rather than registering the address. The same technique could be used by any slave that wants to keep the address stable for more than one cycle.

Another example would be the address decode within the interconnect. The result of the address decode can be used to determine whether or not the interconnect will allow an address to be passed to a slave. If the address were allowed to change this would force the address decode to occur in a single cycle.

A third example would be a clock domain boundary. If the address is not guaranteed stable then it would always be necessary to place a holding register before the clock boundary, adding an extra cycle.

Article last edited on: 2008-09-09 15:47:44

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