|ARM Technical Support Knowledge Articles|
Applies to: AXI
Verification of AXI components is a significant task which cannot be covered in full detail here, but one useful hint is to make sure that during simulation signals (such as address and control signals) are driven with random values whenever they are not required to be set in a valid state.
This may be best avoided for initial debugging purposes as it can make the waveforms confusing. However, when dealing with more mature IP, enabling this feature will enhance any verification performed on an AXI port and may well give improved RTL code coverage in the process.
Article last edited on: 2008-09-09 15:47:44
Did you find this article helpful? Yes No
How can we improve this article?