ARM Technical Support Knowledge Articles

Are there any issues with exclusive accesses passing from one width of data bus to another?

Applies to: AXI


It is recommended that the restrictions listed below are used when generating exclusive AXI bursts. This ensures that the address transaction remains as a single transaction even if processed by certain AXI interconnect blocks such as a downsizer (for connecting a wide bus to a narrower bus)

  • If the burst type FIXED is used, then the length must be no greater than 1 (AxLEN=0). This ensures that any downsizer component will not split the burst into multiple bursts on the narrower bus.
  • If the burst type is WRAP or INCR then it is recommended that the total size be no greater than 16 bytes (e.g. length 4 for 32-bit bus, length 2 for 64-bit bus). This ensures that the burst can always be downsized to a single burst on a narrower bus (the limit being a length 16 burst on an 8-bit bus).
  • If the system design is known, then the maximum allowable total size of an exclusive burst must be defined as 16x the width (in bytes) of the narrowest bus which will carry exclusive accesses.

Article last edited on: 2008-09-09 15:47:45

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