ARM Technical Support Knowledge Articles

How does a SWP operation on a CPU translate in to bus activity?

Applies to: AXI


A SWP operation will result in a locked sequence of a read transaction followed by a write transaction to the same address.

An interesting case to note is that if an error is received on the read operation the processor must perform another AXI transaction in order to complete the locked sequence and unlock the interconnect for other masters to use. In most cases it is likely that the locked sequence will be completed with a write transaction which has no write strobes asserted.

Article last edited on: 2008-09-09 15:47:45

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