ARM Technical Support Knowledge Articles

If a slave receives three addresses from different masters M1, M2 and M3 in that order and has an interleaving depth of 3 can the slave expect to see any data from M3 before it sees data from masters M1 and M2?

Applies to: AXI


The protocol requires that the first item of write data is received in the same order as the addresses and therefore before the master receives any write data from M3 it must have received at a minimum the first data items from both M1 and M2.

Article last edited on: 2008-09-09 15:47:45

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