ARM Technical Support Knowledge Articles

How should a 32-bit write accesses across a 64-bit bus be represented as AXI transactions?

Applies to: AXI

Answer

If the access is word aligned then it could be performed using a burst of length 1 and size 32-bit, all the strobes within this container will be asserted. If the access is not word aligned, but does not cross a 64-bit boundary then it could be performed using a burst of 1 length and size 64-bit, this access will only have 4 out of the possible 8 strobes asserted. If the access is across a 64-bit boundary then it could be performed using a burst of length 2 with size 32.

This is just a recommendation on how the access should be performed, but it is not the only legal way in which the transaction can occur. For example, it would be correct protocol to perform a 32-bit burst of length 2 in all cases and just assert the strobes as required, which in some cases would mean that all the strobes are de-asserted for one of the two data transfers.

 

Article last edited on: 2008-09-09 15:47:45

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential