ARM Technical Support Knowledge Articles

Why are the read and write address buses defined with all four bits of ACACHE. Does a read transaction need to give the write allocate information and vice versa?

Applies to: AXI

Answer

The reason for including read and write allocation on both read and write address buses is that it allows a system level cache to optimise it performance. For example, if a cache sees a read access that is defined as "write allocate, but not read allocate" then it knows that the address may actually be stored in the cache (because it could have been allocated on a previous write) and hence it must do a cache lookup. However, if the cache sees a read access that is defined as "no write allocate and no read allocate" then it knows that the address will not have been allocated in the cache and hence it can avoid the cache lookup and immediately pass the transaction through to the other side. It can only do this if it knows both the read and write allocate for every transaction.

It is not a requirement that caches operate in this way, but the protocol is defined with RA/WA for both reads and writes to allow this mode of operation if the cache designer wants to implement it.

Article last edited on: 2008-09-09 15:47:45

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential