ARM Technical Support Knowledge Articles

Why does my debugger fail to return ETM Trace from the PB926 and AB926?

Applies to: AB926, PB926, RealView Development Suite (RVDS)


[updated 25 April 2007]

This FAQ is relevant if you are attempting to collect Trace (using the AXD or RVD debuggers) from the ARM PB926EJ-S and AB926EJ-S Versatile family development boards.

Due to the timing of the trace signals inside the ARM926EJ-S development chip, code cannot be traced at more than 140MHz. This happens in both normal and half-rate tracing modes. By default, the ARM926EJ-S core clock is set to 210MHz.

We can now offer customers using RealView Trace (RVT) units a hardware fix. Please contact your local ARM sales office or distributor, quoting your RVT serial number, then we will send you an 'inverted trace probe' free of charge. This probe uses the falling edge of the trace clock instead of the rising edge.

Otherwise, if you want to trace your code, you need to reduce the core clock frequency down to 140MHz or less. This can be done by unlocking the system registers (writing 0xA05F to SYS_LOCK) and modifying the value of SYS_OSC0. By default, the core clock is programmed to be 6 times faster than the OSC0 clock, so a core clock running at 140MHz can be obtained by setting SYS_OSC0 = 0x00002C6C.

You can adjust the default core clock speed using either debugger CLI commands or by adding appropriate code to your applications reset handler.

  1. Setting the core clock frequency using RVD script commands:

    setmem /32 0x10000020 =0x0000A05F
    setmem /32 0x1000000C =0x00002C6C
    setmem /32 0x10000020 =0x00000000

  2. Setting the core clock frequency using AXD script commands:

    setmem 0x10000020 0x0000A05F 32
    setmem 0x1000000C 0x00002C6C 32
    setmem 0x10000020 0x00000000 32

  3. Equivalent ARM assembler code:

    SYSLOCK EQU 0x10000020
    SYS_OSC0 EQU 0x1000000C

    LDR r0,= SYSLOCK    ; Read unlock register address
    LDR r1,= 0x0000A05F ; Unlock the System Registers
    STR r1,[r0]         ; Write unlock value
    LDR r0,= SYS_OSC0   ; Read oscillator register address
    LDR r1,= 0x00002C6C ; Load value for 140MHz
    STR r1,[r0]         ; Write oscillator value
    LDR r0,= SYSLOCK    ; Read unlock register address
    LDR r1,= 0x00000000 ; Lock the System Registers
    STR r1,[r0]         ; Write unlock value

Article last edited on: 2009-01-20 17:39:41

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