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Using CT926 + PB926: How do I identify which core is which on the JTAG scan chain?

Applies to: CT926, PB926

Answer

When using the Application Note 125 with a CT926EJ-S Core Tile and  a PB926EJ-S, there will be two ARM926EJ-S cores in the JTAG chain.  This FAQ is intended to make it clear which one you are connecting to when using our Multi-ICE and RealView ICE tools.

The Multi-ICE numbers TAP with reference to TDI while the RealView ICE numbers TAP in reference to TD0. Hence with Multi-ICE, the ARM926 core on the Core Tile is recognized at TAP0  (on the left) and at TAP1 when using the RealView ICE.

Multi-ICE
The Auto Configure function of the Multi-ICE Server recognizes the ARM core on the Core Tile at TAP0 (on the left) and the ARM core on the PB926EJ-S at TAP1, as shown below:

Multi-ICE Server

TAP 0 is the Core Tile processor
TAP 1 is the PB926EJ-S processor

In the RVD connection window shown below you can see two ARM cores. Each core is suffixed with the TAP number of that core (ARM926EJ-S_0 and ARM926EJ-S_1).

Multi-ICE Connection

ARM926EJ-S_0 -TAP 0 is the Core Tile processor, the suffix 0 is the TAP number
ARM926EJ-S_1 -TAP 1 is the PB926EJ-S processor, the suffix 1 is the TAP number

RealView ICE
The Auto Configure function of the RVConfig always recognizes the ARM core on the PB926EJ-S at TAP0 and the ARM core on the Core Tile at TAP1.

RVConfig

TAP 0 is the PB926EJ-S processor
TAP 1 is the Core Tile processor

In the RVD connection window shown below you can see two ARM cores.  Each core is suffixed with the TAP number of that core (ARM926EJ-S_0 and ARM926EJ-S_1):

RVI Connection

ARM926EJ-S_0 -TAP 0 is  the PB926EJ-S processor, the suffix 0 is the TAP number
ARM926EJ-S_1 -TAP 1 is the Core Tile processor, the suffix 1 is the TAP number

Related Download

PDF Icon Application Note 125 

Attachments: img12577.jpg , img12576.jpg , img12574.jpg , img12575.jpg

Article last edited on: 2009-01-20 13:56:13

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