ARM Technical Support Knowledge Articles

What are the restrictions when debugging the ARM968E-Srd core?

Applies to: DSTREAM, RealView Development Suite (RVDS), RealView ICE and Trace (RVI / RVT)


The ARM968E-Srd is a reduced debug core which does not implement hardware breakpoints or single stepping logic. See related FAQ: What are the debug options on the ARM968E-S? 

This means that it is not possible to single step or set breakpoints in ROM. However, DSTREAM / RVI is able to single step and set breakpoints in RAM using software breakpoint instructions. Note that if the instruction you are stepping generates an abort, the core will run, unless a breakpoint is also manually placed on the abort vector.

Article last edited on: 2011-11-02 17:06:15

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