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How do I change the clock frequencies on the CT1136?

Applies to: CT1136


Some details about the ARM1136JF-S Core Tile clock circuits are not in the current release of the Core Tile user guide. This FAQ describes the clock circuit on the ARM1136JF-S Core Tile and test chip, how to change the frequencies, and includes a small program to measure the core frequency.

To change the clocks you need to know about three areas:

  • The test chip clock circuit, described below

The CT1136JF-S Core Tile can be used with a PB926EJ-S Platform Baseboard and a Logic Tile, using the example design we provide in application note AN125. We also provide example designs for using a Core Tile with a Logic Tile and IM-LT1 (AN136), Core Tile with IM-LT3 (AN138), and Core Tile with EB (AN148); but their clock circuits are not discussed here. This FAQ uses AN125 as an example.

AN125 board-level clock routing
The diagram below shows the CT1136JF-S Core Tile clock signals used in AN125. Default clock frequencies and multiplexer settings are shown. The clock circuit inside the ARM1136JF-S test chip is described in more detail later.

AN125 Clock architecture diagram THUMBNAIL

(Click on thumbnail for full-size diagram)

ARM1136 test chip internal clock circuits
This diagram shows the clock circuit inside the ARM1136JF-S test chip. The default clock frequencies, divider and multiplexer settings for AN125 are shown:

CT1136JF-S / AN125 test chip clocks diagram THUMBNAIL

(Click on thumbnail for full-size diagram)

It is possible to change the test chip internal divider and multiplexer settings via memory mapped control registers, as shown in the diagram. The clock control register addresses for AN125 are:

Register Address
CT_OSC 0x10400008
CT_LOCK 0x10400014
CT_AUXOSC 0x1040001C
CT_INIT 0x10400024
Clock Generator Control Register 0x3F200080

CT_OSC, CT_AUXOSC and CT_INIT are locked from accidental changes by the CT_LOCK register. Write 0x0000A05F to CT_LOCK to unlock them, and any other value to lock them. You must preserve the original values of bits you are not writing to (read-modify-write the register).

Changes to the clock dividers for CLK, HCLKI or HCLKE take place immediately. If you are using the ARM1136JF-S in asynchronous mode (CPU asynchronous to bus ports), you must make sure changes to these dividers propagate before selecting the asynchronous ratio. HCLKI must be an integer multiple of HCLKE. In ARM1136JF-S synchronous mode (the default), CLK must be an integer multiple of HCLKI greater than 1. These clocking modes are selected via static configuration pins on the ARM1136JF-S core. For more information on this functionality, please refer to the ARM1136JF-S TRM.

Changes to PLLREFDIV, PLLFBDIV and PLLOUTDIV take place after a soft reset. That is, when you press the reset button S2 on the PB926EJ-S. Reads from the CT_AUXOSC register (PLLOUTDIV and PLLREFDIV control bits) will not show the updated values until a soft reset has occurred.

All divider ratios are (register value + 1). For example, a PLLOUTDIV value of 0 means divide by 1, a value of 1 means divide by 2.

Measuring the core frequency
A utility is provided here to enable a quick check of the ARM1136JF-S core clock frequency. The utility comprises two stand-alone AXF programs which must be run in sequence:

  • Using the debugger, load and run InitTCM.axf to initialise the ARM1136JF-S Tightly Coupled Memory (TCM). This program only needs to be run once per debug session, unless the TCM settings are subsequently changed by another program
  • Next, load and run Speedtest.axf. This program was linked to be loaded (by the debugger) into TCM as configured in the previous step.

Speedtest.axf executes 1,000,000 loops that each take 20 core clock cycles on an ARM11. It measures how long the whole operation takes, using a counter clocked at 24MHz. The final count value is left in register R3. Results from our test board (with the default AN125 frequencies) are show below as an example:

R3 = 0x001E8486 = 2,000,006 counts

1 count = 1 / 24MHz = 41.67ns

Total program execution time = 2,000,006 x 41.67ns = 83.33ms

Core frequency = total cycles / total time = 20,000,000 / 83.33ms = 240MHz

Attachments: img13539.gif , img13540.gif ,

Article last edited on: 2009-01-20 14:09:02

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