Many customers want to use a Core Tile mounted on their own custom motherboard to implement a system which has an architecture that more closely matches their final ASIC.
Please note that Core Tiles are not a stand-alone product, they are designed to be used with our other development boards using the example designs we provide in our application notes. Application Notes 125, 136 and 138 may be of particular relevance:
Which application notes work with which boards?
We are only able to offer limited support for such design activity, namely the contents of this FAQ. If you choose to build a custom motherboard for a Core Tile then we recommend you use one of our example designs as a starting point. The following is a list of areas you should pay particular attention to:
- A Core Tile needs both 3V3 and 5V supply rails. The test chip VDDCORE supply is derived from the 5V rail
and VDDIO from the 3V3 rail. Typical current consumption is detailed in the CT user guides.
- Your custom board must have adequate power supply decoupling.
- The core voltage is set for your test chip by a manufacturing option and can be varied by a programmable DAC within safe limits of around +/- 20% using a serial data stream from an adjacent board. AN125 includes software and RTL that does this.
- The system level reset circuit and timing diagrams are documented for our baseboards, for example in the IM-LT3 user guide. The application note RTL also demonstrates this.
- Core Tiles do not have a clock generator so your custom board must supply a low-jitter clock. Your timing scheme must ensure low skew between the core clock and buses. We recommend you base your clocking scheme on our example designs.
- We cannot guarantee the maximum clock frequency of test chips since we get them from various partners. You should use the default speeds as set in our example designs as a starting point. Even these may not be suitable from some operating conditions.
- Test chip clock circuits and instructions for changing frequency are documented in the Core Tile user guides and example designs. If you are using the ARM1136JF-S Core Tile see this FAQ:
How do I change clock frequencies on the ARM1136JF-S Core Tile?
- Clock selection is done by the Core Tile PLD during power-up, as configured by the serial data stream. You should use the serial stream generation RTL we provide in the application notes.
- Core Tiles contain no working memory system; they merely present the test chip raw AMBA bus signals (either AHB or AXI) at the header connectors. In order for the ARM test chip on the Core Tile to run code, or even for a debugger to be connected, the Core Tile must be connected to a working AMBA bus. The exact elements required will depend on whether the test chip has an AHB or AXI interface. We suggest you use the most relevant app note for an example of a working memory system.
- JTAG connectivity to a Core Tile should be provided by the board below it. Each ARM tile board has the ability to loop back the JTAG signals to the board(s) below, if it detects that it is the board at the top of the stack. This functionality is documented in the user guides.
- To minimize the risk of faults in the JTAG circuitry, and to ensure the debug connection to the ARM core runs as fast as possible, we recommend that you do not daisy-chain the Core Tile JTAG signals with TAPs on your custom board.
- Please see our JTAG related articles under Multi-ICE and RealView ICE articles.
- Static configuration signals such as VINITHI should be setup as in our app note RTL, for example AN138.
- The Core Tile user guide does not document some signals used to validate the ARM core inside the test chip. For example: USERIN[5:0] and USEROUT[5:0]. Copy how they are connected from our example design.
- Some test chips such as ARM1136JF-S load configuration data via the data bus on reset. This is not explained in the user guides, but it can be seen in our example design RTL.
- Some test chips have different bus configuration options. You should use the default from our example design.
- We do not have test chip signal timing information. The only exception is the ARM11MPCore test chip, whose AXI bus timing is documented in the ARM11MPCore Core Tile user guide. When the boards were designed, a degree of trial and error was required to select the timing constraints for our example designs (see the .ucf and .ncf files).
- The Core Tile user guides include a mechanical drawing, which is generally not suitable for PCB connector placement. To position the SAMTEC connectors on your PCB you should use the exact dimensions from the Gerber files we provide:
PCB Data: CT7TDMI, CT926EJ-S, CT1136JF-S, CT11MPCore
- If you require clarification on a particular functional area, the schematics and PCB netlist are an excellent source of information. These files are accessible from the 'PCB Data' URL above, and should be used in conjunction with the RTL and pin constraints files in our example designs to get a full understanding of system operation.
- A useful design checking exercise is to make a list all of the pins on all of the Core Tile header connectors (many signals are a direct connect between the upper and lower connectors) and check each off in turn, when you are satisfied that you have connected each pin (or group of pins) to the appropriate circuitry. This will help ensure that no signals are left unconnected, or connected inappropriately.