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Applies to: CT926
The test chips used on the CT926EJ-S Core Tile have an internal interrupt controller, which sits between the test chip nIRQ and nFIQ pins and the corresponding interrupt inputs on the ARM core itself. To enable interrupts on these test chips you must either:
If you have RealView Debugger (RVD) then you can use 'vector_catch' in the RVD register window to trap the IRQ and FIQ exceptions. You must also have interrupts enabled in the CPSR (Current Program Status Register) in the ARM core.
Article last edited on: 2009-01-20 14:01:53
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