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Older CM1136JF-S boards will not boot with FPGA image 'RevD build7'

Applies to: Integrator

Answer

[New 11 July 2006]

This FAQ applies to some older (circa early 2005) CM1136JF-S boards with the following test chip fitted; specifically when the CM is fitted to an Integrator/CP motherboard:

Line drawing of ARM1136 test chip with non-functional PLL

Symptoms

If a Core Module fitted with this test chip is used in conjunction with an incompatible FPGA image (such as the CP image, RevD build7), the board will not come out of reset and the development system will be rendered temporarily unusable. Symptoms are that the alpha-numeric LED display on the CP motherboard does not show the usual 'CP' text, and the 'MISC' LED on the Core Module will not light, despite the Boot Monitor switches being set to the correct positions (S1-1, S1-4 = ON).

This situation typically arises when a customer wishes to update their Core Module to the latest available FPGA image, not knowing that the latest version will not work with this specific test chip type.

Solution

For the Integrator/CP, the latest FPGA image that can be used with this test chip type is 'RevD build4'. This is because the PLL in the '0344' test chip is unusable and must be disabled by the FPGA. This is described on the printed Release Notes document that is shipped with these boards. Please see FAQ: CM1136JF-S internal PLL and SRAM for further information.

Later test chips with a functional PLL component (see drawing below) can make use of the later FPGA image (RevD build7), which enables the PLL by default. Build 4 and build 7 are identical, except for the default state of the PLL after a power-on reset.

Drawing of later ARM1136JF-S test chip with functional PLL:

Line drawing of ARM1136 test chip with functional PLL

Background information

As is the case with many ARM development boards, the CM1136JF-S can be built with test chips from various silicon manufacturers. There may be distinct differences in features between test chips from different batches (for example the lack of a PLL). Please see the FAQ: Features and performance of ARM Test Chips are subject to change.

Note that both test chip types will function correctly with the latest Integrator/AP CM FPGA image - RevB build 3.

Article last edited on: 2009-02-10 17:33:15

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