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Applies to: Versatile Logic Tiles
This FAQ only applies to the RVI version of progcards.
We have discovered that some versions of the Xilinx FPGA bit file generation tools can produce a larger .bit file than we have seen before. If you are generating a .bit file for a Logic Tile based on the XC2V8000 FPGA, this can cause programming to fail, as the RVI hardware cannot accept the size of file. The displayed error will be similar to:
ERROR: Communication error with RealView ICE: "XXXXXXXXX" (exec)
Please reboot your RealView ICE and try again
The ability to download larger FPGA images will be addressed in a future release of progcards. As a work-around, turning on .bit file compression in the Xilinx tools will reduce the file size, and allow programming to work.
Article last edited on: 2009-01-20 18:22:14
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