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Can I stack a Logic Tile on (Integrator CP + IM-LT3 + CT)?

Applies to: Integrator, LT-XC2V (Virtex-II)

Answer

[New 15 Aug 2006]

It is possible to build a development system comprising the following boards:

Basic stack block diagram CP+IM-LT3+CT+LT

A pre-built binary FPGA image for the IM-LT3, which allows the boards to be stacked in this manner can be obtained here. The RTL source code and project files for the IM-LT3 in this configuration are provided only on the CD-ROM that ships with the CP board. This configuration is documented in Appendix C of the IM-LT3 user guide, which can be accessed from this page. Instructions for programming and setting up this stack of boards can be found in another FAQ.

It is possible to add one or more  Logic Tiles to the stack, in order to prototype AHB bus slaves. The existing IM-LT3 RTL source code does not provide an interface from a Logic Tile to the Integrator/CP System Bus. To implement this interface, several configuration/connection issues must be addressed. It is also possible to add bus masters to the system, but a different bus architecture should be used. These issues and options are described in detail below.

In this configuration, the IM-LT3 performs four main functions:

  • Allows a Core Tile to be mounted on a CP motherboard, since the connectors are physically different 
  • Provides the control logic for the peripheral interfaces on the CP motherboard
  • Provides the interface between the CT7TDMI test chip Local Bus and the CP AHB-Lite System Bus
  • Provides the JTAG connection to all boards in the stack

The following is a list of the areas which must be addressed to enable a Logic Tile to operate on top of this stack. These points should be read in conjunction with the diagram at the end of this FAQ. The existing documentation (circuit schematics and netlists, user guides and RTL source) should also be used to gain a full understanding of the issues involved.

1. Z-Bus Break switches on the IM-LT3

The Z[127:0] bus on the IM-LT3 and CT can be used to connect the Integrator/CP A,B,C,D (Address, Control, Peripheral, Data) buses up to the LT FPGA on the top of the stack.

To complete this signal path, the Z-Bus break switches for (at least) the A,C and D buses on the CT and IM-LT3 must be set to CLOSED.

On the IM-LT3, this is done by changing the supplied RTL source (imlt7tdmi.v) so that at power-on, the control PLD on the IM-LT3 is sent the correct control data for its ZCTL[3:0] outputs. Sending the parameter ZTHRU instead of ZBRK will close the switches and pass the signals up to the CT:

 // Constant declarations for control PLD

  parameterZTHRU       = 4'b0000;
 parameter ZBRK        = 4'b1111;

  parameterRTCK_ON     = 1'b0;
  parameterRTCK_OFF    = 1'b1;

 // Edit this line to set FOLD / THRU setup
 parameter PLD_DATA = {RTCK_ON, ZTHRU};

Ideally, the 'B' bus should not be enabled, since this will unnecessarily send many LCD controller signals up to the top of the stack. The  Z-Bus and ZCTL pins on the IM-LT3 are mapped as follows:

Z-Bus

Integrator Bus

ZCTL

Z[127:96]

A[31:0]

0

Z[95:64]

B[31:0]

1

Z[63:32]

C[31:0]

2

Z[31:0]

D[31:0]

3

 

 

 

 Z-Bus, ABCD buses and ZCTL mapping on IM-LT3

So, to break only the B-Bus, the ZCTL[3:0] value should be 4'b0010:

 parameter PLD_DATA = {RTCK_ON, 4'b0100};

Note that the ZCTL[3:0] signals on the IM-LT3 are also connected to the YU[43:40] pins on the upper header connector, but there is nothing on the CT which can drive these; they pass straight through the CT. The LT above the CT could drive them, if the necessary signal/pin assignments were made in that FPGA. This would help remove the need to rebuild the IM-LT3 FPGA. Be careful that both boards do not drive this signal, since FPGA damage could occur.

2. Bus Break switches on the Core Tile

The corresponding Z-Bus break switches on the CT must also be closed to complete the signal path. This is controlled by the PLD on the Core Tile, and the serial configuration parameters for this PLD are sent by the board below the CT - in this case the IM-LT3. The operation of this PLD is described in the CT user guide.

The serial stream logic that drives the CT PLD is in imlt7tdmi.v, but the ZCTL value is fed in to that module from a memory-mapped register, defined in cp7tdmi_141b_regs.vhd:

 -- Set CT PLD configuration information
  SetCoreTilePLD: process(PCLK,PORESETn)
  begin
    if (PORESETn= '0') then
      CTPLDReg(3downto0)  <= "1111"; -- the system starts with all Z isolated

Perhaps the simplest way to change this ZCTL value is to get the ARM application code to write to the 'CTPLDReg ' register at 0x10000094. However, if a permanent change is required (and this is advisable), it will be necessary to modify the VHDL and change the reset default value, so that the system powers up with the correct value in this register. Note that the ZCTL to Z-Bus mapping is different between the CT and the IM-LT1 boards:

Z-Bus

ZCTL

Z[127:96]

3

Z[95:64]

2

Z[63:32]

1

Z[31:0]

0

 

 

 Z-Bus and ZCTL mapping on a Core Tile

 

Thus, a ZCTL value of 4’b0100 would break only the B-Bus. If the B-Bus is broken in the IM-LT3, it is not strictly necessary to also break it on the Core Tile.

If the application software configures the Z-Bus switches, care must be taken that no accesses to the Logic Tile address space (0xD0000000+) can occur before the bus is connected, else the Logic Tile slaves will not respond and the System Bus will lock up.

3. Disable 'Default Slave' response from motherboard for LT address range

The Flash/Ethernet controller PLD on the CP motherboard is responsible for providing the default slave (Abort) response on the System bus for the three unused 256MB Logic Module regions at 0xD0000000, 0xE0000000 and 0xF0000000.

If  System Bus slaves are being added in the Logic Tile, the default slave response on one or all of these ranges must be disabled, so that the LT slaves can respond at these addresses.

This is done by grounding one or more of the nEPRES[3:0] lines into the motherboard PLD. On the IM-LT3, these are connected to signals YU[123:120] and the existing RTL source imlt7tdmi.v already grounds nEPRES(0):

  assignYU[120]    = 1'b0; //nPPRES0

To open up extra address ranges for the logic tile slaves, simply add extra assignments for signals YU[123:121] as required:

 assign YU[121]    = 1'b0; //nPPRES1 - 256MB @ 0xD0000000
 assign YU[122]    = 1'b0; //nPPRES2 - 256MB @ 0xE0000000
 assign YU[123]    = 1'b0; //nPPRES3 - 256MB @ 0xF0000000

Since these signals are routed up the stack to the LT, it is also possible to drive them from the LT, which would help remove the need to modify and rebuild the IM-LT3 FPGA.

Note - The RevA IM-LT3 board also inadvertently shorts the nPPRES0 line to GND, since pins 33 and 34 on HDRB (J7) are swapped in the PCB design. If the nPPRES signal is driven LOW or set to Hi-Z in the LT or IM-LT3 FPGA, no damage will occur. Be careful that neither FPGA drives this signal to HIGH, as this will almost certainly cause damage to these FPGA I/Os. Please see Related FAQ for more information.

4. AHB Clock

The LT slaves require an AHB bus clock (HCLK). This should be supplied from the CP baseboard on either the SYSCLK1 or SYSCLK3 signals. These appear at the LT FPGA as CLK_IN_MINUS1 and CLK_IN_MINUS_2 respectively.

5. AHB slave connection logic

The Integrator/CP System Bus uses a tri-state implementation of AHB. Applications Note 119 can be used as an example of how to connect the bus slaves to the System Bus.

Note - The AN119 image will not work if it is simply programmed into an LT and connected on top of this board stack.

6. Bus masters

It is possible to add bus masters to the system, but a different bus architecture would be required, since the Integrator/CP uses the AHB-Lite bus protocol, which allows only one bus master (the ARM CPU core). One way to add bus masters in a Logic Tile would be to instantiate a bridge in the IM-LT3 FPGA, and splitting the Z[127:0] bus at the IM-LT3. The custom masters (and slaves) could then exist on the upper segment of this bus, and the Integrator/CP's AHB-Lite System bus would continue to exist on the lower segment of the bus.

System block diagram - adding an LT to (CP + IM-LT3 + CT) stack

Attachments: img14127.gif , img14270.gif

Article last edited on: 2009-01-20 15:16:06

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