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Problems connecting a JTAG ICE to an IM-LT3 + LT platform

Applies to: Integrator, LT-XC2V (Virtex-II)

Answer

The IM-LT3 board can be used with one or more Logic Tiles to build a custom development system containing a synthesized processor core and peripherals. Some customers have reported problems connecting JTAG debug tools to such systems.

Symptoms: When using an IM-LT3 with one or more stacked Logic Tiles, a JTAG ICE unit cannot AutoConfigure the scan chain, nor can a debugger be reliably connected to a manually configured scan chain. Reducing the TCK speed may improve JTAG operation.

Cause: The nMBDET and nRTCKEN signals are used on the IM-LT3 to decide whether RTCK (Return TCK) to the JTAG ICE should be looped back inside the IM-LT3, or passed down to the board below. If there is no board below, nMBDET should be a logic '1', which allows the IM-LT3 RTCK loopback switch to be closed, dependant on the state of nRTCKEN. This is shown in the diagram below:

Block diagram IM-LT3 + LT - Driving RTCK (thumbnail) (Click on image to enlarge)

If the FPGA pins that connect to the nMBDET signal are left undeclared in the RTL code on both the IM-LT3 and Logic Tile, the Place & Route tool assigns these pins to be connected to a weak pull-down. With two such pull-downs in place, the 10k pull-up on the PCB is sometimes insufficient to keep the input to the inverter as a '1'. Whenever nMBDET is a '0', the RTCK loopback switch is forced open; regardless of the state of nRTCKEN. This can cause the JTAG connectivity problems described above.

Solution:

Add a PULLUP attribute to the nMBDET pin in the .UCF (User Constraints File) for either the IM-LT3 or LT FPGA project. This will remove the weak pull-down and replace it with a pull-up, which reinforces the pull-up on the IM-LT3. Note that it may be necessary to also declare the nMBDET signal as an input in the FPGA RTL and route it to some dummy logic, to prevent the FPGA tools from optimising away an unused input. Alternatively nMBDET could be declared as a tri-state output and permanently disabled:

 nMDBET <= 'Z' when (ALWAYS_ONE = '1') else '0';

This makes use of a signal called ALWAYS_ONE, whose state will always be a logic '1' so long as the FPGA is configured. This signal is usually already present in ARM Logic Tile FPGA example designs.

It is also possible to fix this problem by declaring the nMBDET signal as an output in one of the FPGAs, and assigning it the value '1'. This is not an advisable solution, since any ARM motherboard inserted below the IM-LT3 will short this signal to the 0V supply rail. This would almost certainly destroy the I/O pad driver on the attached FPGA. Such damage would not be covered under warranty.

Attachments: img14155.gif

Article last edited on: 2009-01-20 15:28:36

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