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Which AN152 (Using a CT11MPCore with the EB) FPGA, PLD and PDF versions should I use?

Applies to: CT11MPCore, EB (Emulation Baseboard)


[Updated 22 March 2007]

Application Note 152 provides pre-built FPGA binaries which allow a CT11MPCore Tile to be used with an Emulation Baseboard (EB). It also includes a PDF document describing some of the system architecture and memory map. Several revisions of the EB have been sold since its introduction. Only revisions C and onwards are fully supported, with proper documentation. Please see the related FAQ for more information on the differences between RevB systems and those released since.

Depending on which version of the boards you have, you will need to use a different combination of FPGA and PLD images, and consult a different document to get the correct information about the system architecture. The FPGA/PLD images and PDF documentation are supplied on a CD-ROM that ships with the boards. The various versions of the AN152 PDF do not state internally which FPGA build they relate to.

The relationships between FPGA, PLD image versions and PDF versions is depicted in the following table. Clicking on the items in the 'PDF version' column will start a download of that version of the document.

EB PCB version

CT PCB version

FPGA version

CT PLD version

PDF version







First release of AN152.

C or D

C or D




Released on the Versatile 3.0 and 3.0.1 CDs. The RevB document covers the build C1 FPGA image, but there are several minor errors. It should be discarded and the RevC-01 document used instead.


The RevC-01 draft document contains much improved information on system clock architecture, default clock settings and memory mapped registers.




Document updated to include new features of the build C4 FPGA image.




Released on the Versatile 3.1.1 CD for the 'with PCI' build. Only recommended for PCI development.




Released on the Versatile 3.1.1 CD for the 'no DMA/PCI' and 'with DMA' builds. Timing problems are fixed.

Even though FPGA images C1 through C7 are compatible with EB versions RevC and RevD, your set of pre-defined boardfiles may prevent you from using every version with your board. For example, if you use CFG PLD build 3 on a RevC baseboard or CFG PLD build 2 on a RevD baseboard, the Ethernet interface will not function. Therefore, you should only choose menu options that match your board PCB versions.

ispClock Settings

The CT11MPCore employs two ispClock 5620 ICs for clock signal distribution. These hold non-volatile timing parameters, which can be programmed via the JTAG scan chain using Progcards. From time to time, ARM releases updated settings for these devices. To ensure your system is operating with the highest stability, you should be using the latest configuration (Build 3). To add this option to the Progcards programming menu, you should merge these boardfiles into your existing AN152 boardfiles directory structure.

Differences between CD-ROM versions

Depending on which version of the CD-ROM you have, the pre-defined Progcards 'boardfiles' supplied on the CD-ROM may or may not automatically reprogram the PLDs on the EB to be compatible with each FPGA image version. You may also need to manually reprogram the PLD on the CT11MPCore Tile to maintain compatibility with the reprogrammed motherboard.

CD-ROM 3.0 users

This CD version contains AN152 FPGA build C1, EB CFG PLD build2, CT11MPCore PLD v7. It is therefore only suitable for RevC systems and there should be no incompatibility issues between the EB FPGA/PLD and CT11MPCore PLD versions. The AN152 FPGA boardfile automatically programs the EB CFG PLD and prompts the user to program the CT11MPCore PLD.

CD-ROM v3.01 users

This CD contains AN152  FPGA build C1, and is suitable for use with RevC and RevD systems.

The boardfiles for programming the EB FPGA, EB CFG PLD and CT11MPCore PLD are in separate folders, and the AN152 boardfiles do not automatically program the EB CFG PLD. It is therefore necessary to run Progcards from three separate locations in order to program all devices to a compatible standard. If installed to the default locations, these folders are:

  • C:Program FilesARMApplication_NotesAN1523.01evAoardfiles - AN152 EB FPGA images
  • C:Program FilesARMVersatileEB3.01Releaseoardfiles - EB CFG PLD images
  • C:Program FilesARMVersatileCT11MPCore3.01Releaseoardfiles - CT11MPCore PLD images

Note: There are .brd scripts in the AN1523.01evAoardfiles folder which cause Progcards to display menu choices for programming FPGA builds B29 and B30 and the CT11MPCore PLD. However, the binary images are not present under this directory tree, so these options will not work. Run Progcards again from the CT11MPCore3.01Releaseoardfiles folder to program the Core Tile.

CD-ROM v3.1.1 users

This CD-ROM contains four AN152 FPGA builds: C1, C6 (the only build with PCI) and C7 (both with DMA and without DMA). Progcards menu options exist to program any of these builds into either a RevC or RevD system.

The pre-defined AN152 boardfiles on this CD not only program the EB FPGA but also reprogram the EB’sConfig PLD’ version to support the particular Ethernet MAC chip used on an EB. Progcards will also prompt the user to reprogram the PLD on the CT11MPCore board.

As an illustration, both the following Progcards menu options select the same FPGA image, but different Config PLD images:

AN152 CTMPCore + Emulation Baseboard Rev C with PCI Little Endian Build 6, PLD Mux build 2, CFG PLD build 2

AN152 CTMPCore + Emulation Baseboard Rev D with PCI Little Endian Build 6, PLD Mux build 2, CFG PLD build 3

How to identify the board, FPGA and PLD versions in your system

  • The EB PCB version is written in copper on the corner next to the 16x2 character LCD. The version is a letter at the end of this number, for example, HPI-0140C means you have a rev C board.
  • The CT11MPCore PCB version is also written in copper on a corner. Again, HPI-0146C means you have a rev C board.
  • The Boot Monitor should display the FPGA version on the 16x2 character LCD a few seconds after power up. For example, H/W: C 1 means FPGA version C1. The FPGA version number is contained in bits [7:0] of the SYS_ID register at 0x10000000.
  • The Core Tile PLD version number can be read from bits [3:0] of the SYS_PLD_CTRL2 register at 0x10000078.
  • It is not possible to read the version number of any of the other PLDs in the system or the ispClock devices on the CT. The only way to be sure of which versions are programmed is to reprogram the devices with a known image version.

Further Notes

Article last edited on: 2009-01-20 14:50:50

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