ARM Technical Support Knowledge Articles

Using CT11MPCore + EB: How are interrupts routed?

Applies to: CT11MPCore, EB (Emulation Baseboard)

Answer

[New 20 September 2006]

The Emulation Baseboard (EB) user guide and application note AN152 do not correctly explain interrupt routing with the ARM11 MPCore Core Tile. The tables below show the correct interrupt routing into the pins on the MPCore test chip. This information applies to the EB FPGA image provided in AN152 version C1.

AN152 supports three interrupt modes, and you can enable the nFIQ interrupts for each mode. These modes are selected using the INTMODE[2:0] field in the EB's SYS_PLD_CTL1 register. To configure interrupts you must also write to other registers in the EB and MPCore.

You should refer to the EB user guide and AN152 for other details.

Legacy mode

This mode supports the MPCore 'legacy ARM interrupts' mode, which uses the legacy nIRQ pins instead of the MPCore's Interrupt Distributor. This mode is the default and is used to run the boot monitor on CPU 0. To select this mode set INTMODE[2:0] = X00, where X=1 enables or  X=0 disables the nFIQ inputs.

 Interrupt source  MPCore input  EB tile site 1 signal
 COMMRX0 †  INT0 ‡  Z200
 COMMRX1 †  INT1 ‡  Z201
 COMMRX2 †  INT2 ‡  Z202
 COMMRX3 †  INT3 ‡  Z203
 COMMTX0 †  INT4 ‡  Z204
 COMMTX1 †  INT5 ‡  Z205
 COMMTX2 †  INT6 ‡  Z206
 COMMTX3 †  INT7 ‡  Z207
 0  INT8 ‡  Z208
 0  INT9 ‡  Z209
 0  INT10 ‡  Z210
 0  INT11 ‡  Z211
 GIC2  INT12 ‡  Z212
 GIC4  INT13 ‡  Z213
 MCIINTR0  INT14 ‡  Z214
 MCIINTR1  INT15 ‡  Z215
 GIC1  nIRQ0  Z208
 GIC3  nIRQ1  Z209
 USBnINT  nIRQ2  Z210
 AACIINTR  nIRQ3  Z211
 GIC2 *  nFIQ0  Z212
 GIC4 *  nFIQ1  Z213
 MCIINTR0 *  nFIQ2  Z214
 MCIINTR1 *  nFIQ3  Z215

* if FIQs enabled using INTMODE2 = 1, otherwise the nFIQ is logic 1

† these DCC interrupts are input to the EB FPGA but not used

‡ not used by the MPCore in legacy ARM interrupts mode

New mode with DCC

New mode uses the MPCore's Interrupt Distributor and DCC stands for 'Debug Communications Channel'. DCC enables you to communicate with your application using JTAG, without stopping the processor. To select this mode set INTMODE[2:0] = X01, where X=1 enables or X=0 disables the nFIQ inputs.

 Interrupt source  MPCore input  EB tile site 1 signal
 AACIINTR  INT0  Z200
 TIMERINT01  INT1  Z201
 TIMERINT23  INT2  Z202
 USBnINT  INT3  Z203
 UARTINT0  INT4  Z204
 UARTINT1  INT5  Z205
 RTCINT  INT6  Z206
 KMIINT0  INT7  Z207
 COMMTX0  INT8  -
 COMMTX1  INT9  -
 COMMTX2  INT10  -
 COMMTX3  INT11  -
 GIC2  INT12  Z212
 GIC4  INT13  Z213
 MCIINTR0  INT14  Z214
 MCIINTR1  INT15  Z215
 COMMRX0 †  nIRQ0  -
 COMMRX1 †  nIRQ1  -
 COMMRX2 †  nIRQ2  -
 COMMRX3 †  nIRQ3  -
 GIC2 *  nFIQ0  Z212
 GIC4 *  nFIQ1  Z213
 MCIINTR0 *  nFIQ2  Z214
 MCIINTR1 *  nFIQ3  Z215

* if FIQs enabled using INTMODE2 = 1, otherwise the nFIQ is logic 1

the MPCore Interrupt Distributor presents these as INT31

New mode without DCC

This mode uses the MPCore's Interrupt Distributor. We recommend you use this mode for symmetric multi-processing (SMP) to get the maximum benefit from the MPCore. To select this mode set INTMODE[2:0] = X10, where X=1 enables or X=0 disables the nFIQ inputs.

 Interrupt source  MPCore input  EB tile site 1 signal
 AACIINTR  INT0  Z200
 TIMERINT01  INT1  Z201
 TIMERINT23  INT2  Z202
 USBnINT  INT3  Z203
 UARTINT0  INT4  Z204
 UARTINT1  INT5  Z205
 RTCINT  INT6  Z206
 KMIINT0  INT7  Z207
 KMIINT1  INT8  Z208
 ETHINTR  INT9  Z209
 GIC1  INT10  Z210
 GIC3  INT11  Z211
 GIC2  INT12  Z212
 GIC4  INT13  Z213
 MCIINTR0  INT14  Z214
 MCIINTR1  INT15  Z215
 1  nIRQ0  -
 1  nIRQ1  -
 1  nIRQ2  -
 1  nIRQ3  -
 GIC2 *  nFIQ0  Z212
 GIC4 *  nFIQ1  Z213
 MCIINTR0 *  nFIQ2  Z214
 MCIINTR1 *  nFIQ3  Z215

* if FIQs enabled using INTMODE2 = 1, otherwise the nFIQ is logic 1

Article last edited on: 2009-01-20 16:21:15

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential