Why do ARM recommend a minimum of 12x difference between SSPCLK and SSPCLKIN in the slave?
Applies to: PL022 Synchronous Serial Interface
Answer
This figure of 12x is to ensure that we can detect an edge of SSPCLKIN half way through its transfer. Synchronisation logic takes three SSPCLK cycles, leaving a margin of 25% of the SSPCLKIN cycle for skew/data hold.
Article last edited on: 2008-09-09 15:47:49
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