|ARM Technical Support Knowledge Articles|
Applies to: PL022 Synchronous Serial Interface
This figure of 12x is to ensure that we can detect an edge of SSPCLKIN half way through its transfer. Synchronisation logic takes three SSPCLK cycles, leaving a margin of 25% of the SSPCLKIN cycle for skew/data hold.
Article last edited on: 2008-09-09 15:47:49
Did you find this article helpful? Yes No
How can we improve this article?