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Applies to: PL08x DMAC (DM & SM)
The peripheral is usually used as the flow controller in situations where the packet length is unknown at the time when the DMA channel is enabled.
For instance, a UART, say, could initiate data transfers to and from memory (or some other peripheral) as and when it chooses by asserting the BREQ, SREQ, LBREQ and LSREQ signals to the DMAC. The DMAC then responds by transferring the data. The timing of the transfers, however, is controlled entirely by the UART.
The DMAC is used as the flow controller when the packet length is known at the time the channel is enabled and also where the peripherals concerned are not capable of making their own decisions as to when data is transferred.
Article last edited on: 2008-09-09 15:47:49
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