|ARM Technical Support Knowledge Articles|
[Updated 24 November 2006]
The ARM11 MPCore can run at 620MHz on 90nm silicon, but please note our development boards are significantly slower. This is because:
We provide an FPGA image for EB rev C and D boards in application note AN152. See the FAQ here for details of the AN152 versions available.You must set the EB clock configuration switches correctly before power-on. Here are the default settings you must use as a starting point:
The table below shows the default clock frequencies for these switch settings. We do not have any specific figures for bus throughput.
|MPCore and L2 cache||200MHz a||210MHz b||175MHz a||210MHz d|
|MPCore to EB AXI bus (tile site 1)||20MHz a||30MHz b||25MHz a||30MHz d|
|AXI bus matrix in EB FPGA||35MHz||30MHz b||25MHz c||30MHz d|
|DDR SDRAM||30MHz||30MHz||25MHz c||30MHz|
|Logic Tile AXI bus (tile site 2)||10MHz||24MHz||25MHz||25MHz|
a MPCore, L2 cache and AXI bus clocks are synchronous.
b MPCore, L2 cache, AXI bus and bus matrix clocks are synchronous.
c Bus matrix and DDR SDRAM clocks are synchronous.
d MPCore, L2 cache, AXI bus and bus matrix are synchronous.
All other clocks are asynchronous. Note that transactions between asynchronous clock domains have additional clock cycle(s) inserted.
Article last edited on: 2009-01-20 14:47:28
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