ARM Technical Support Knowledge Articles

How fast is the CT11MPCore + EB platform?

Applies to: CT11MPCore, EB (Emulation Baseboard)


[Updated 24 November 2006]

The ARM11 MPCore can run at 620MHz on 90nm silicon, but please note our development boards are significantly slower. This is because:

  • the test chip on the CT11MPCore Core Tile was not made using 90nm.
  • samples of the test chip have been tested successfully at 260MHz, but we cannot guarantee the maximum operating frequency for all test chips.
  • the L2 cache on the test chip has a maximum operating frequency of 215MHz.
  • the Emulation Baseboard (EB) includes an AXI bus matrix implemented in an FPGA, which is not as fast as an ASIC.

We provide an FPGA image for EB rev C and D boards in application note AN152. See the FAQ here for details of the AN152 versions available.You must set the EB clock configuration switches correctly before power-on. Here are the default settings you must use as a starting point:

  • for AN152 version C1 and C4 set switch S8-5 OFF and S8-6 ON. Set all the other configuration switches (S6, S8, S10) to OFF (UP).
  • for AN152 version C6 and C7 set switch S8-6 OFF. Set all the other configuration switches (S8-5,S6, S8, S10) to OFF (UP). Please note in these versions S8-5 no longer controls the clocks and should be set to OFF (UP).

The table below shows the default clock frequencies for these switch settings. We do not have any specific figures for bus throughput.

 C1  C4  C6  C7
 MPCore and L2 cache  200MHz a  210MHz b  175MHz a  210MHz d
 MPCore to EB AXI bus (tile site 1)  20MHz a  30MHz b  25MHz a  30MHz d
 AXI bus matrix in EB FPGA  35MHz  30MHz b  25MHz c  30MHz d
 DDR SDRAM  30MHz  30MHz  25MHz c  30MHz
 Logic Tile AXI bus (tile site 2)  10MHz  24MHz  25MHz  25MHz

a  MPCore, L2 cache and AXI bus clocks are synchronous.

b  MPCore, L2 cache, AXI bus and bus matrix clocks are synchronous.

c  Bus matrix and DDR SDRAM clocks are synchronous.

d  MPCore, L2 cache, AXI bus and bus matrix are synchronous.

All other clocks are asynchronous. Note that transactions between asynchronous clock domains have additional clock cycle(s) inserted.

Article last edited on: 2009-01-20 14:47:28

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