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What is the clock architecture of the CT7TMDI + IM-LT3 + Integrator CP platform?

Applies to: CT7TDMI, Integrator

Answer

[New 21 Sep 2006]

It is possible to build a development system comprising: Integrator/CP + IM-LT3 + CT7TDMI, stacked as shown in the diagram below.

A pre-built binary FPGA image for the IM-LT3, which allows the boards to be stacked in this manner can be obtained here. The RTL source code and project files for the IM-LT3 in this configuration are provided only on the CD-ROM that ships with the CP board. This configuration is documented in Appendix C of the IM-LT3 user guide, which can be accessed from this page. Instructions for programming and setting up this stack of boards can be found in another FAQ.

The user documentation does not describe the specifics of the system clock architecture for this ARM7TDMI system. Trying to deduce the clock architecture from the RTL source files can be confusing, since this system FPGA is based on RTL that was written for an ARM926EJ-S test chip, supported by a Logic Tile. This means that there is some redundant source code in the main VHDL file (cp7tdmi_141b_fpga.vhd) and a layer of signal name translation, which is provided by the file imlt7tdmi.v.

The following diagram shows the clock architecture of the example system, comprising CP + IM-LT3 + CT7TDMI:

CP + IM-LT3 + CT7TDMI System clocks block diagram (Thumbnail)  [Click on diagram to enlarge]

Core Tile Clock Multiplexing - Default Settings

The configuration PLD on the Core Tile (not shown in diagram) controls the routing of clock signals between adjacent boards. A diagram of this can be found in the Core Tile user guide, in the 'HBI-0141 Hardware Description' section. The default setting for the clock multiplexors is to route the XL[32] signal through to the X_MCLK_UP signal and through to the MCLK input on the test chip.

Changing the Clock SpeedUnderSoftware Control

The CM_OSC register at 0x10000008 controls the speed of the ARM7TDMI core and system bus, which run at the same speed. The OSC2 oscillator is the source for these clocks. The input from this oscillator is divided by two as it enters the FPGA, so the default oscillator output of 40MHz gives a core/bus speed of 20MHz.

To change the core/bus clock speed, the following procedure should be used:

  • Enable changes to the CM_OSC register by writing 0xA05F to the CM_LOCK register at 0x10000014
  • Write the new clock speed value into bits [7:0] of the CM_OSC register, as per the equation or table below. Note that reading back the CM_OSC register contents at this time will still show the old value.
  • Make the changes take effect by performing a 'soft reset' of the system. This can be done by pushing the reset button (nPB / S2) on the IM-LT3 or by writing a '1' to bit 3 of the CM_CTRL register at 0x1000000C.
  • Confirm that the system is still functional at the new clock frequency. Note that at the upper and lower limits, operation may become unstable - you should select a clock frequency that is 'safely' inside the operational limits. The table below lists typical limits.

Calculating Clock Speed Settings for the CM_OSC Register

The following equations and worked examples give the oscillator output frequency (fosc) and core/bus frequencies (MCLK and HCLK) for a given set of oscillator control values:

  fosc = 48 * (VDW + 8) / ((RDW + 2) * OD))

  fosc = 48 * (32 + 8) / ((22 + 2) * 2)

  fosc = 40MHz

  MCLK = HCLK = fosc / 2

  MCLK = HCLK = 20MHz

For this system, the parameters in the above equation are derived thus:

  • VDW = CM_OSC[7:0] - Default is 0x20 in FPGA:

constant CM_CPU_VDW_VAL :std_logic_vector(7downto0) := "00100000";

  • RDW = 0x16 - Hard-wired in FPGA:

R_UpllC <= "0010110";

  • OD = 2 - Hard-wired in FPGA:

S_UpllC <= "001"; -- A value of '1' means 'divide by 2' (see ICS307 datasheet for further information)

Note that the values that are visible in bits [31:8] of the CM_OSC register are remnants of the ARM926EJ-S heritage that this example system was based on, and have no relevance whatsoever to the CT7TTDMI system.

Table of Common Clock Frequencies

 CM_OSC[7:0]

Frequency (Core/bus)

 Notes

0x13

13.5MHz

Typical minimum - *See note below

0x20 

20MHz

Power-on default frequency

0x30

28MHz

Typical maximum

 

 

 

 

* Note - The DLLs in the FPGA require a certain minimum input frequency to achieve lock. This sets the minimum clock frequency for the system. Operating frequency limits will depend on various factors such as component manufacturing tolerances and ambient temperature.

System Expansion

In the diagram above, it can be seen that the system bus can be extended up the stack, for connection to custom slaves in Logic Tiles for example. By default, the ZCTL bus switches are open and the system bus is not passed up the stack. For details on how to add Logic Tiles to this system, please see this related FAQ.

Attachments: img14704.gif

Article last edited on: 2009-01-20 13:47:42

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