ARM Technical Support Knowledge Articles

Why does the LCD have random pixels?

Applies to: Versatile Baseboards

Answer

[updated 21 January 2008]

Pixels appearing at random and in short horizontal lines (known as 'tearing') is caused by bus bandwidth and arbitration limitations making the Color LCD Controller (CLCDC) FIFO intermittently run empty.

Depending on your platform and memory configuration, here are some points to try:

  • If you are using 24-bit color mode (24 bits per pixel), then try using 16-bit color. In 24-bit mode only one pixel is stored per word, whereas 16-bit mode has two pixels per word and uses half the bandwidth.

  • On most boards the CLCDC has the highest priority to access SDRAM, but the ARM processor can keep hold of the bus for several cycles when doing load multiple (LDM) or store multiple (STM) instructions. Compilers generate LDM and STM to push and pop data to the stack for function calls. You can remove the random pixels by running the processor out of cache or TCM.

  • We do not recommend using the 2M byte SSRAM on the PB1176, PB926, AB926 or EB as a frame buffer. This is because the PL093 synchronous static memory controller Primecell used is an early version: changing the byte lanes in a burst access can write the wrong data. You must insert wait states to work around this.

  • If you are using the Emulation Baseboard (EB) with an ARM1136JF-S or ARM926EJ-S Core Tile then bus bandwidth is much lower than other boards. The ARM11 MPCore Core Tile has more bus bandwidth available for CLCDC than other Core Tiles on the EB, thanks to its 64-bit AXI bus and 1M byte L2 cache.

  • If you have implemented a graphics engine in a Logic Tile then you could use its SSRAM or block RAM as a frame buffer. This will give you a little more bandwidth and remove contention from processor accesses.

  • If you are using Linux and the right-hand edge of the screen is wavy, this is caused by clock jitter. There is a patch to fix this.

  • You can change the CLCDC FIFO 'watermark' level from 4 to 8. The CLCDC reads data until it fills the FIFO above the programmed watermark. Set the PL111 LCD Control Register bit 16 to 1.

You can download example software for our LCD panels from our website here.

For more details about bus bandwidth see our Versatile performance FAQ.

Article last edited on: 2009-01-20 11:24:46

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